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1、DesigningwithQuartusIIObjectivesCreateaNewQuartusIIProjectCompileaDesignintoanFPGALocateResultingCompilationInformationAssignDesignConstraints(Timing&Pin)PerformTimingAnalysis&ObtainResultsCreateSimulationWaveform&SimulateaDesignConfigureanFPGA2ClassAgendaProjectsExercise1DesignMethodo
2、logyinQuartus®IIExercise2CompilationExercise3Single&Multi-ClockTimingAnalysisExercise4&5SimulationExercise6Programming/ConfigurationExercise7or83DesigningwithQuartusIIIntroductiontoAltera&AlteraDevicesIntellectualProperty(IP)SignalProcessingCommunicationsEmbeddedProcessorsNios®IIDevice
3、s(continued)MAX®IIMercury™DevicesACEX®DevicesFLEX®DevicesMAXDevicesToolsQuartus®IISoftwareSOPCBuilderDSPBuilderNiosIIIDEDevicesStratix®II™Cyclone™IIStratixGXStratixCycloneTheProgrammableSolutionsCompany®5StructuredASICHardCopy®II,HardCopyStratixHigh&MediumDensityFPGAsStratix™II,Stratix
4、,APEX™II,APEX20K,&FLEX®10KLow-CostFPGAsCyclone™II&CycloneFPGAswithClockDataRecoveryStratixGX&Mercury™CPLDsMAX®II,MAX7000&MAX3000EmbeddedProcessorSolutionsNios™II,Excalibur™ConfigurationDevicesSerial(EPCS)&Enhanced(EPC)ProgrammableLogicFamilies6Software&DevelopmentToolsQuartusIIAllStrat
5、ix,Cyclone&HardcopyDevicesAPEXII,APEX20K/E/C,Excalibur,&MercuryDevicesFLEX10K/A/E,ACEX1K,FLEX6000DevicesMAXII,MAX7000S/AE/B,MAX3000ADevicesQuartusIIWebEditionFreeVersionNotAllFeatures&DevicesIncludedSeewww.altera.comforFeatureComparisonMAX+PLUS®IIAllFLEX,ACEX,&MAXDevices7DesigningwithQ
6、uartusIIQuartusIIDevelopmentSystemFeatureOverviewQuartusIIDevelopmentSystemFully-IntegratedDesignToolMultipleDesignEntryMethodsLogicSynthesisPlace&RouteSimulationTiming&PowerAnalysisDeviceProgrammingMoreFeaturesMegaWizard®&SOPCBuilderDesignToolsIncrementalDesignFlowLogicLock™Optimizati
7、onToolPowerPlayPowerAnalyzerToolNativeLink®3rd-PartyEDAToolIntegrationDebugToolsSignalTap®IISignalProbe™In-SystemMemoryContentEditorWindows,Solaris,HPUX,&LinuxSupportNode-Locked&NetworkLicensingOptions10QuartusIIOperatingEnvironmentProjectNavigatorStatusWindowMessageWindow11MainToolb
