[信息与通信]cadence实验系列13_rtl编译和束缚_rcandec

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1、Cadence实验系列13_RTL编译和束缚_RTLcompiler&Encounterconformal2010.12.23RTLcompiler(RC)IntroductionRoleinICdesignGUIinterfaceSynthesisflowIntroductionRCisafast,highcapacitysynthesissolutionfordemandingchipdesigns‘Globalfocusedsynthesis’resultsinrapidtimingclosureIntrod

2、uction综合是前端设计的重要步骤HDL代码翻译成门级网表netlist约束条件（达到面积，时序等参数标准）需特定工艺库评价标准：面积，速度，功耗SynthesistoolIC设计综合工具包括SynopsisDC和CadenceRC；在FPGA端，常用的综合工具有Synplicitysynplify和XilinxXSTSynthesis综合的过程分为两步，首先将HDL描述语言翻译成与工艺库无关的门级网表文件，然后通过综合工具优化，映射到跟具体工艺库相关的门级网表。RTLcompiler(RC)Introductio

3、nRoleinICdesignGUIinterfaceSynthesisflowRoleinICdesign前端设计规格制定详细设计HDL编码仿真验证逻辑综合ICprocessAdvantage时序收敛的全局综合工具提高芯片性能缩短设计时间提供高质量的硅片（Qos）RTLcompiler(RC)IntroductionRoleinICdesignGUIinterfaceSynthesisflowStartGUI命令符：rc-guiGeneralViewManubarLogicalviewerHDLviewerSche

4、maticviewerPhysicalviewerManubarManubarLogicalviewerandHDLvewerSchematicviewerRTLcompiler(RC)IntroductionRoleinICdesignGUIinterfaceSynthesisflowSynthesisflowInvoketheRCSpecifythelibraryLoadHDLfilesPerformElaborationApplyconstraintsSynthesizeSavedesignAnalyzeSyn

5、thesisflowset_attributelib_search_path/set_attributehdl_search_pathset_attributelibrary/read_hdlelaboratesetclock[define_cloc

6、k–period–name[clock_ports]]external_delay–inputexternal_delay–outputsynthesize-to_mappedreporttiming>reportarea>

7、a_report_file_name>write–mapped>write_script>Step1InvoketheRCrc－guiStep2Specifythelibrary设置工艺库存放路径set_attributelib_search_path/export/home1/STSY_BB/BB_y29/lib/Synopsys指定要加载的工艺库set_attributelibrary{hjtc18_tt.lib}Step3LoadH

8、DLfilesLoadMipssourcesread_hdl/export/home1/STSY_BB/BB_y29/mips_source/MCore.vread_hdl/export/home1/STSY_BB/BB_y29/mips_source/alu_v2.vread_hdl/export/home1/STSY_BB/BB_y29/m