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1、实用标准文案libraryieee;useieee.std_logic_1164.all;entityfpqisport(fsin:instd_logic;Preset:instd_logic_vector(3downto0);clk:instd_logic;dout:outstd_logic_vector(31downto0);seltmp:outstd_logic_vector(7downto0);smtmp:outstd_logic_vector(6downto0));end;architectureartoffpqiscomponentcnt10port(clk,clr
2、,ena:instd_logic;cq:outstd_logic_vector(3downto0);carry_out:outstd_logic);endcomponent;componentreg32bport(load:instd_logic;din:instd_logic_vector(31downto0);dout:outstd_logic_vector(31downto0));endcomponent;componenttestctlport(clk:instd_logic;tsten,clr_cnt,load:outstd_logic);endcomponent;c
3、omponentdeccountPort(inclk:instd_logic;Preset:instd_logic_vector(3downto0);--y_tmpdiv,y_tmpclk:outstd_logic;Outclk:bufferstd_logic);endcomponent;--componentzmjsxs--port(ck:instd_logic;--data:instd_logic_vector(31downto0);--sel:outstd_logic_vector(7downto0);--sm:outstd_logic_vector(6downto0))
4、;--endcomponent;signaltsten:std_logic;signalclr_cnt:std_logic;signalload:std_logic;signalcarry1:std_logic;signalcarry2:std_logic;signalcarry3:std_logic;文档实用标准文案signalcarry4:std_logic;signalcarry5:std_logic;signalcarry6:std_logic;signalcarry7:std_logic;signalcarry8:std_logic;signaldin:std_log
5、ic_vector(31downto0);signaloutclk:std_logic;signalfsintmp:std_logic;signaldouttmp:std_logic_vector(7downto0);beginfsintmp<=fsin;dout<=douttmp;u:deccountportmap(inclk=>fsintmp,preset=>preset,outclk=>outclk);u0:testctlportmap(clk=>clk,tsten=>tsten,clr_cnt=>clr_cnt,load=>load);u1:cnt10portmap(c
6、lk=>outclk,clr=>clr_cnt,ena=>tsten,cq=>din(3downto0),carry_out=>carry1);u2:cnt10portmap(clk=>carry1,clr=>clr_cnt,ena=>tsten,cq=>din(7downto4),carry_out=>carry2);u3:cnt10portmap(clk=>carry2,clr=>clr_cnt,ena=>tsten,cq=>din(11downto8),carry_out=>carry3);u4:cnt10portmap(clk=>carry3,clr=>clr_cnt,
7、ena=>tsten,cq=>din(15downto12),carry_out=>carry4);u5:cnt10portmap(clk=>carry4,clr=>clr_cnt,ena=>tsten,cq=>din(19downto16),carry_out=>carry5);u6:cnt10portmap(clk=>carry5,clr=>clr_cnt,ena=>tsten,cq=>din(23downto20),carry_out=>carry6);u7:cnt10portmap(
