64进制bcd码计数器vhdl设计

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1、二、64进制BCD码VHDL设计1.实体框图CLKQ22[3..O]Q11[3..0lr0CU'54A^//////////////^///////////////^2.程序设计LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNS1GNED.ALL;ENTITYCDU_64AISP0RT(CLK:INSTD_L0GIC;Q22:OUTSTD_L0GIC_VECT0R(3D0WNT00);Q11:OUTSTD_L0GIC_VECT0R(3DOWNTO0));ENDCDU_64A;ARCHIT

2、ECTUREAAOFCDU_64AISSIGNALCOUT2,COUT1:STD_L0GIC_VECT0R(3DOWNTO0);BEGINPROCESS(CLK)BEGINIF(CLK*EVENTANDCLK三1*)THENIF(COUT2=6ANDCOUT1=3)THENCOUT2v=”0000”；COUTl<=”0000”;ELSIF(COUT1=9)THENCOUT2v=COUT2+1;COUT1<=n0000H;ELSECOUT2<=COUT2;COUT1<=COUT1+1;ENDIF;ENDIF;ENDPROCESS;Q22<=COUT2;Q11

3、<=COUT1;ENDAA;3•仿真波形图MasterTimeBar:17.025rNameValueet1703nsCLKB01□Q22U0i田QUU0Start:81.57us0p$End:°

4、彳Pointer:81.59usInterval:)ps10.罕g20・£8u,30J2u.40.9,6w51冷“61・申271.6,8w81军u,92.甲"17.025nshWi*血山汕1山1山I山I山111山I山I山111山皿山I山加加III山I山1山1山1山11期4.仿真波形分析由图可知，elk为上升沿时计数。该程序设计为64进制BCD码。三、64进制二进

5、制码VHDL设计1.实体框图CDU54ECLKQ[7・・0]irst2.程序设计LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYCDU_64BISPORT(CLK:INSTD_LOGIC;Q:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCDU_64B;ARCHITECTUREBBOFCDU_64BISSIGNALCOUT2,COUT1:STD_LOGIC_VECTOR(3DOWNTO0);BEGINPROCESS(CLK)BEGI

6、NIF(CLK*EVENTANDCLK三1*)THENIF(COUT2=4ANDCOUT1=15)THENCOUT2<=uOOOO,,;COUTK=,,OOOOm;ELSIF(COUT1=15)THENCOUT2v二COUT2+1;COUT1v二”0000”；ELSECOUT2v=COUT2;COUT1v二COUT1+1;ENDIF;ENDIF;ENDPROCESS;Q<=COUT2&COUT1;ENDBB;1.仿真波形图MasterTimeBar10575ns十

7、Pointer:105u$IntervalStart:EndValueat1058ns)ps

8、10.24us20.48us3072us40.96us10.575ns51辛us61.44us716Sus81.92ns92.16usCLK[±]QlRrLrumnnjvuTmuLruTn_njmnnnjmrLrumnnjvuTrmjvuTrLnjmarLnjmnjTr1111■111111111112.仿真波形分析由图可知，elk为上升沿时计数。该程序设计为64进制二进制码。