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1、实验十四VHDL程序设计及文本文件输入练习一、实验目的1、掌握MaxplusII工具软件的操作2、熟练掌握VIIDL程序设计3、熟练掌握VHDL文本文件输入操作方法二、实验内容1、掌握VH叽编程要求、规则及结构（参考课件）2、掌握MaxplusIII具软件进入文本输入工作区3、输入VIIDL程序，编译、仿真、建立图形符号•3/8译码器P108CASElibraryieee;useieee.std_logic_1164.all;entitydecoderisport(signalsekinstd_logic_vector(2downto0)
2、;signalen:instd」ogic;signaly:outstd_logic_vector(7downto0));enddecoder;architecturebehaviorofdecoderisbeginprocess(sel,en)beginy<=nllllllir,;if(en='T)thencaseseiiswhenM000H=>y(0)<=,0,;whenn00r,=>y(l)<=,0,;when,,010,,=>y(2)<=,0,;whenn011n=>y(3)<=,0,;when,,100n=>y(4)<=,0,;w
3、hen,,10r,=>y(5)<=,0,;whenT10”=>y(6)v=O；whennlir,=>y(7)<=0,;whenothers=>null;endcase;endif;endprocess;endbehavior;•七段译码器P109libraryieee;useieee.std_logic_1164.all;useiee.std_logic_arith.all;entitybedisport(d:instd_logic_vectoe(3downto0);en:instd_logic;data_out:outstd_logic
4、_vector(7downto0));endbed;architecturebedofbedisbeginprocessbeginif(en-r)thencasediswhenn0000"=>data_out<=n00111111";whenn0001n=>data_out<=n00000110";when"0010"=>data_out<=,,0lOllOir*;whenu0011”=>data_outv二”01001111”；whenn0100"=>data_out<="01100110n;whenn0101M=>data_out<=
5、n01101101";whenK0110H=>data_out<=n0111110r*;when"0111"=>data_out<=M00000111when"1000n=>data_out<=n01111111";when"l001"=>data_out<=,'01100111'*;whenothers=>data_out<="11111111";endcase;endif;endprocess;endbed;•十进制计数器P117三、1、实验步骤选择文本文件输入区File/NewVHDL,进行文本文件输入，并保存注意（与实体名一致）2
6、、选择当前工程File/Project；编译或MaxplusII/Computer选器件Assign/device3、管脚分配MaxplusII/fro,如下图，确定工程、编译•filAX*plusII-d:tigcrdccodcr-[(CurrentAssignments)-FloocplanEditor]匚回冈SAX^plusIIEileEditLayoutAssignytilitiesOptionsJihdovHelp-ffX03耳k?金段蜀qd妙闔淹is歳用兮IS2二ChipName：
7、decod©r(EPF10K10LC84
8、-3)ColofLegend口Unassigned■Unrouted■NonassignableLlnossigncdNodes&Piru:口Row1Col.FastTrack/DedicatedInputIBRowFastTrackOColumnFostTrockQ744Q750Q756Q:762SelectedNode(s
9、&Pin(s):(IO)E16(10)^17(IO)匚18(IOU19(2匚25(GNDINT)・26(IQ)J27(IQ)匚28(IO匚29/••—70二HIO・RDYnBUSY)69ZJIIO.IN
10、IT_DOME)68HlGHDINTl67□
