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1、答案由个人整理，难免有错，仅供参考！！！一、单项选择题：上课讲到的其它知识点，如变量与信号的含义；进程的含义；eda开放流程等；有两三道可能有一定难度。二、名词解析：ASIC：专用集成电路、FPGA：现场可编程门阵列、IP：知识产权核或知识产权模块、JTAG：联合测试行动组、I1DL：硬件描述语言、SOPC：可编程片上系统、PCB：(ProcessControlBlock)进程控制块、RTL：寄存器传输级、LPM：可设置模块库、CPLD：复杂可编程逻辑器件、FSM：有限状态机三、简答题：课本第一、二章后的简答
2、题；另耍明白自顶向下设计方法的优缺点。简答题：第一章的:1-2.1-4.1-5以及“要明白自顶向下设计方法的优缺点”有可能会考，已经去除了两道题目。第二章的：2-2>2-4(已经去除三道题目)PS：以上信息是在EDA课程答疑时，老师透露出来的，没有在的题FI肯定不会考。答案自己在书上找，byxw.四、VHDL程序改错题：主要偏重语法。五、编程器：组合逻辑电路：38译码和83编码38译码：libraryieee;useieee.std_logic_l164.all;entityDECODERisPORT(A,B
3、,C:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(7DOWNTO0));endDECODER;architectureAofDECODERisSIGNALINDATA:STD_LOGIC_VECTOR(2DOWNTO0);BEGININDATA<=C&B&A;PROCESS(INDATA)BEGINCASEINDATAISWHEN”000”二〉YVOOOOOOOl”；WHEN,,oor,=>Y<=,,ooooooion；WHEN,,010M=>Y<="00000100H;WHEN”01
4、l”=>Y<=“00001000”；WHEN”100”=>Yv=”00010000”;WHEN,,10r,=>Y<=,,00100000n;WHEN,,110n=>Y<=H01000000n;WHEN"lir,=>Y<=n10000000";WHENOTHERS=>Yv=”00000000”；ENDCASE;ENDPROCESS;endA;83编码libraryieee;useieee.std_logic_1164.all;entityencodeisport(d:instd_logic_vector(7do
5、wnto0);ein:instd_logic;aOn,a1n,a2n,gsn,eon:outstd_logic);endencode;architecturebehavofencodeissignalq:std_logic_vector(2downto0);begina0n<=q(0);a1n<=q(1);a2n<=q(2);process(d)beginifein-1'thenq<="111M;gsn<='l';eon<='1';elsifd(7)=,0'thenq<=H000,,;gsn<=,0,;eon
6、<=,r；elsifd(6)=,0'thenqv二”00r,;gsn<=,0,;eon<=,1*;elsifd(5)='O'thenq<=H010n;gsn<=,0,;eon<=,1*;elsifd(4)=,0,thenq<=H011n;gsn<=*0';eon<='1*;elsifd(3)='O*thenq<="100";gsn<='0';eon<-1elsifd(2)=,0,thenq<=M10r,;gsn<=,0,;eon<=,r；elsifd(l)=,0'thenq<=,,110,,;gsn<=,0,
7、;eon<=,r；elsifd(0)=,0,thenq<=H111,F;gsn<=,0,;eon<='1*;elsifd=ull111111"thenqv=”lll”；gsnv=T；eonv=’0‘；endif;endprocess;endbehav;时序逻辑电路：同步计数器与异步计数器（要明白两种计数器的差异）同步计数器：LIBRARYIEEE;-带时钟使能的同步4位二进制减法计数器；useIEEE.STD_LOGIC_1164.ALL;useieee.std_logic_unsigned.all;ENTI
8、TYcountISPORT(clk,clr,en:INSTD_LOGIC;qa,qb,qc,qd:OUTSTD_LOGIC);ENDcount;ARCHITECTUREbehavOFcountISSIGNALcount_4:STD_LOGIC_vector(3DOWNTO0);BEGINQa<=count_4(0);Qb<=count_4(l);Qc<=count_4(2);Qd<=count_4(
