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1、Chapter21DesignandDevelopmentofStress-EngineeredCompliantInterconnectforMicroelectronicPackagingLunyuMa,SureshK.Sitaraman(*ü),QiZhu,KevinKlein,andDavidFork21.1IntroductionPowerandlatencyarefastbecomingmajorbottlenecksinthedesignofhighperform-ancemicrop
2、rocessorsandcomputers.Powerrelatestobothconsumptionanddissipa-tion,andtherefore,effectivepowerdistributiondesignandthermalmanagementsolutionsarerequired.Latencyiscausedbytheglobalinterconnectsontheintegratedcircuit(IC)thatspanatleasthalfachipedgeduetot
3、heresistancecapacitance(RC)andtransmissionlinedelay[1].Limitstochippowerdissipationandpowerdensityandlimitsonhyper-pipelininginmicroprocessorsthreatentoimpedetheexponentialgrowthinmicroprocessorperformance.Incontrast,multicoreprocessorscancontinuetopro
4、videahistoricalperformancegrowthonmostconsumerandbusinessapplica-tionsprovidedthatthepowerefficiencyofthecoresstayswithinreasonablepowerbudgets.Tosustainthedramaticperformancegrowth,arapidincreaseinthenumberofcoresperdieandacorrespondinggrowthinoff-chi
5、pbandwidtharerequired[2].Thus,itisprojectedbytheSemiconductorIndustryAssociationintheirInternationalTechnologyRoadmapforSemiconductors(ITRS)(Table21.1)thatbytheyear2018,withtheICnodesizeshrinkingto22nmby2016and14nmby2020,thechip-to-substratearea-arrayi
6、nputoutputinterconnectswillrequireapitchof70µm[3].Furthermore,toreducetheRCandtransmissionlinedelay,low-Kdielectric/Cuandultra-low-Kdielectric/Cuinterconnectsonsiliconwillbecomeincreasinglycommon.InsuchICs,thethermo-mechanicalstressesinducedbythechip-t
7、o-substrateintercon-nectscouldcrackordelaminatethedielectricmaterialcausingreliabilityproblems.Flipchipswithsolderbumpsarebeingincreasinglyusedtodaytoaddresstheseneedsbecauseoftheirseveraladvantages:higherI/Odensity,shorterleads,lowerinductance,higherf
8、requency,betternoisecontrol,smallerdevicefootprint,andlowerprofile[4].Flip-chipsonboard(FCOB)aregainingincreasedaccept-ancebothforcost-performanceaswellashigh-performanceapplications.Epoxy-S.K.SitaramanComputer-AidedSimulationofPackagin
