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verilog hdl coding styles for optimal simulation performance

verilog hdl coding styles for optimal simulation performance

ID：33775808

大小：227.16 KB

页数：36页

时间：2019-03-01

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1、ApplicationNoteRev.1.1VerilogHDLCodingStylesforOptimalSimulationPerformanceThemethodsdescribedinthisapplicationnotearedeliberatelybroadandgeneric.Requirementsforyourspecificdesignmaydictatemethodsandstylesslightlydifferentfromthosedescribedhere.PurposeThisapplicatio

2、nnotedescribesguidelinesforwritingVerilogHDLcodethatwillsimulatemostoptimallyinacompiled-codesimulator.Ittellsyouhowto:■Identifysimulationthroughputbottlenecks■WriteVerilogcodethatwillsimulatewiththebestperformance■AvoidVerilogcodewhichwillmostlikelyslowdownsimulat

3、ionTheinformationcoversissueswithcodingofdesignsaswellastestbenches.NC-Verilogwasusedfortesting,butthestylesdescribedshouldboostperformanceofanycompiled-codesimulator.BackPage1CloseCloseCadenceConfidentialVerilogHDLCodingStylesforOptimalSimulationPerformanceAudienc

4、eAudienceThisdocumentisintendedforuserswritingVerilogHDLcodefornewdesigns,aswellasforthosewhowanttoimprovetheperformanceofexistingdesigns.OverviewThisdocumentoutlinessomestrategiesfortuningdesignsforoptimalsimulationperformance.Also,whereappropriate,itwilladdresssy

5、nthesizabilityandcyclesimulationissues.TerminologyThefollowingtermsareusedinthisdocument.ProfileAreportdetailinghowmuchtimeasimulationspentineachareaofadesign.I/OAnyinputoroutputfromaprogram,whetheritbewrittentoorreadfromthescreenorafileondisk.RTLRepresentationofades

6、ignattheregister-transferlevel.BackPage2CloseCloseCadenceConfidentialVerilogHDLCodingStylesforOptimalSimulationPerformanceTerminologyregTheregisterdatatypeusedinVerilogHDL.NotethataregintheVeriloglanguageisdifferentfromahardwareregister.BackPage3CloseCloseCadenceCo

7、nfidentialVerilogHDLCodingStylesforOptimalSimulationPerformanceReferenceSynthesizableVerilogcodewhichisgenerallyacceptedbylogicsynthesistools.Cycle-simulatableVerilogcodewhichconformstothemodellingstyleguideofaparticularcyclesimulationtool.Testbench,testfixtureMecha

8、nismtostimulateandcheckresponseofadesign.DeltacycleAtaparticularsimulationtime,signalvaluesareupdated,thenbehaviorssensitivetothosesignalsareexec

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