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1、一、实验所有程序：modulecnt60(clk,q);inputelk;output[7:0]q;reg[7:0]q；always©(posedgeelk)t)eginq[3:O]=q[3:O]+l;if(q[3:0]==10)
2、beginq[3:0]=0;q[7：4]=q[7：4]+l;endif(q=='h60)q=0;enderidmodulemodulecnt24(clk,q);inputelk;output[7:0]q;reg[7:0]q;always@(posedgeclk)beginq[3:O]=q[3:O]+l
3、;if(q[3:0]==10)beginq[3:0]=0;q[7:4]=q[7:4]+l;endif(q=='h24)q=0;endendmodulemodulecontroIlerCclkfmodefadj,sp9ss9mm,sclk9mclk9hcIk^);inputclkfmode,adjtsp;input[7:0]ss.mm;outputsclktmclkThclk;regsclkfmclkfhclk;regmodedltadjdlftnodedZfadjd2;wiremodeinttadjint;reg[l：0]sta
4、tm;paratmeterSrun=0fSadjh=ltSadjm=2;always@(posedgeelk)//generateposedgeformodeandadjbeginmoded2*modedl;endmodedl=mode;adjd2=adjdl;adjdl=adj;assignassignmod皀intmodedl&~moded2;adjint=adjdl&~adjd2;alwaysbegin@(posedgeelk)case(statm)Srun:beginsclk=sp;if(ss==fh59讦(mm==fh
5、59if(modeint)endSadjh:beginhclk=adjint;if(modeint)endSadjm:beginmclk»adjint;if(modeint)enddefault:beginstatm«Srun;end已ndcaseendendmodule&&sp)mclk=l;elsemclk=0;&Ass==fh59&Asp)hclk«l;elsehclk=0;statm=Sadjh;statm=Sadjm;statm«Srun;modulesecgen(clk,sp);inputelk;outputsp;r
6、egsp;reg[6:0]q;always©(posedgeelk)beginq=q+l；if(q==0)sp=l;elsesp=O;endendmodulemoduletimer(clk,mode,adj,hh,ss,mm);inputelk,mode,adj;output[7:0]ss,mm,hh;wiresp,sclk,mcik,hclk;secgensecgenerater(c1k,sp);controllercontrollerl(clk,mode,adj,sp,ss,mm,sclk,mclk,hclk);cnt60s
7、eccounter(sclk,ss);cnt60mincounter(mclk,mm);cnt24hourcounter(hclk.hh);endmodulemodu"eglwn;dederTc1;0dbdc]edb]O1cco:bJu•••>6e3nco@Ice••7nceden=cedefolololololt;oolloollool1)0ooolllloou1doooooooolla1cbbbbbbbbbbfIbe1)C4444444444dIIdddddddddddeeeeeeeeeee*blOOOOOO'bllllOO
8、l'bOlOOlOO'bOHOOOO'bOOHOOl'bOOlOOlO'bOOOOOll'bllllOOO・bOOOOOOO'bOOHOOO1blllllll0123456789////////////////////endmodulemodulescanner(elk,hh,mm,ss,pos,seg);•inputelk;•input[7:0]hh,mm,ss;output[2:0]pos;output[6:0]seg;reg[2:0]pos;reg[6:0]seg;reg[3:0]currBCD;always@(posed
9、geelk)beginpos=pos+l;if(pos==6)pos=0;endalways@(posorhhormmorss)begincase(pos)0:currBCD=ss[3:01;1:currBCD=ss[7:4];2:currBCD=mm[3:0]
