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1、一、实验目的1.学习FPGA的设计方法;2.掌握利用VerilogHDL设计逻辑电路的能力。二、实验所用组件Basys2开发板(芯片为XC3S100E,封装为CP132)1套。三、实验内容下面是4位二进制数加法器的数据流描述,由于被加数A和加数B都是4位的,而低位来的进位Cin为1位,所以运算的结果可能为5位,用{Cout,Sum}拼接起来表示moduleadder(input[3:0]A,input[3:0]B,inputCin,output[3:0]SUM,outputCoutassign{Cout,SUM}=A+B+Cin;Endmodule四、实验步
2、骤与要求1.创建一个子目录Lab2,并新建一个工程项目NewProjectWizardCreateNewProjectSpecifyprojectlocationandtype.Enteraname,locations,andcommentfortheprojectName:Location:WorkingDirectory:Description:lab2::codingMy_xi1inx_LabVlab2::codingMy一xilinx_LabVlab2Selectthetypeo£top~levelsourcefortheprojectTop
3、-levelsourcetypeHBL▼]MoreInfoNextCancelProjectSettingsSpecifydeviceandprojectproperties.SelectthedeviceanddesignflowfortheprojectMoreInfoCancel2.建立一个VerilogHDL文件,将该文件添加到工程项S中并编译整个项目,查看该电路所占用的逻辑甲元(LogicElements,LE)的数量DeviceUtilization[-]LogicUtilizationUsedAvailableUtilizationHote(s
4、)Humberof4inputLUTs41,9201%NumberofoccupiedSlices29601%NumberofSlicescontainingonlyrelatedlogic22100%NumberofSlicescontainingunrelatedlogic020%TotalHumberof4inputLUTs41,9201%HumberofbondedIOBs148316%AverageFanoutofWon-ClockNets1.001.对设计项H进行时序仿真,记录仿真波形图测试代码如下:moduleadd4_tb;//Inputsr
5、eg[3:0]A;reg[3:0】B;regCin;//Outputswire[3:0]Sum;wireCout;//InstantiatetheUnitUnderTest(UUT)add4uut(•A㈧,.Cin(Cin),.Sum(Sum)z.Cout(Cout));initialbegin//InitializeInputsA<=4'dO;B<=4'dO;Cin=l,bO;林1$display("ABCinSumCout=%b%b%b%b%b,,zA,B,Cin/Sum,Cout);A<=4,dO;B<=4,dl;Cin=l'bO;林1$display
6、("ABCinSumCout=%b%b%b%b%b",A,B,Cin,Sum,Cout);A<=4,dO;B<=4,d2;Cin=l,bO;#1$display("ABCinSumCout=%b%b%b%b%bn,A,B,Cin,Sum,Cout);A<=4'dO;B<=4'd3;Cin=l,bO;#1$display("ABCinSumCout=%b%b%b%b%b"/A,B/CinzSum/Cout);A<=4'dO;B<=4,d4;Cin=l'bO;林1$display("ABCinSumCout=%b%b%b%b%b"#A/B/CinzSum#Cou
7、t);A<=4'dl;B<=4,dO;Cin=l'bl;#1$display("ABCinSumCout=%b%b%b%b%b",A,B,Cin,Sum,Cout);A<=4,d2;B<=4,dO;Cin=l,bO;林1$display("ABCinSumCout=%b%b%b%b%b",A,B,Cin,Sum,Cout);A<=4'd4;B<=4,dO;Cin=l'bl;#1$display("ABCinSumCout=%b%b%b%b%b",A,B,Cin,Sum,Cout);endendmodule>.000ns
8、Value0nsns[0000YO00
9、1A0010X0011OOQO
10、4ns111I010