数字逻辑课程实验报告

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1、数字逻辑课程实验报告实验名称存储器部件实验实验人姓名陈根蓉学号406109070219班级计算机科学与技术实验时间2008J2J2成绩石家庄经济学院信工学院一、实验内容1.理解计算机主存储器的分类及作用，掌握存储器的构成。2.掌握ROM,RAM的工作原理及读写方法。二、实验器件厂双极存储器厂随机存储器一1—MOS存储器（胛态.动态｝主存储器_:厂掩模型只读存領器—只读存储器「一可编程只读存储器—町擦编程只读存储器ROM的结构图U■・••••・・••••••••••••••・•••・••••om_memI来一c

2、lockdout[3..0]:■—resetI2■*•2■IinstIRAM的结构图:asynram•e•■■■■•■■■■■■■■■■4"J4■1••1•>•adr[adr_ujidth-1..0]cswrrddin_out[ram_iuidth-1..C]iinstI■■三、实验原理1.系统输入输出确定(1)RAM(16X8)输入输出IN:din,adr,cs,wr,rdOUT:dout(2)ROM(16X8)输入输出IN:clock,resetOUT:dout1.VHDL程序源代码(RAM)RAM存储器LI

3、BRARYIEEE;USEIEEE.STDLOGIC1164.ALL;USEIEEE.STDLOGICUNSIGNED.ALL;MMENTITYasynramISGENERIC(ramwidth:POSITIVE:二8;adr_width:POSITIVE:=4);—2**4X8位的RAMPORT(din:INSTDLOGICVECTOR((ramwidth-1)DOWNTO0);dout:OUTadr:INcs:INwr:INrd:INSTD_LOGTC_VECTOR((ram_width-1)DOWNTO0)

4、;STD_LOGIC_VECTOR((adr_width-1)DOWNTO0);STDL0G1C;STDJ.OGIC;STDLOGIC）；ENDasynrani;ARCHITECTURErtlOFasynramISSUBTYPEramwordISSTDLOGICVECTOR(0TO(ramwidth-1));TYPEram_typeISARRAY(0TO(2**adr_width-1))OFramword;SIGNALram:ramtype;BEGINPROCESS(wr)BEGINIF、vr'EVENTAXDw

5、r-'1'THENIFcs=O'THENram(convinteger(adr))<=din;ENDIF;ENDIF;ENDPROCESS;PROCESS(adr,cs,rd,ram)BEGINIFcs二'O'ANDrd二'O'THENdout<=ram(conv_integer(adr));ELSEdout<=(others=>'Z');ENDTF;ENDPROCESS;ENDrtl;(ROM)ROM存储器PACKAGErompacISCONSTANTrom_width:POSITIVE:二8;CONSTANT

6、adrhigh:POSITIVE:=16;SUBTYPEromwordISbit_vector(0TO(romwidth~l));TYPEromtableTSARRAY(0TO(adr_high-l))OFromword;CONSTANTrom:romtable:二("00000001〃，〃00000010〃，"00000011〃00000100〃，〃00000101〃，"000001io,z,"00000111〃，z，00001000“00001001〃，〃00001010〃，"00001011〃，"000

7、01100〃，"00001101〃，“00001110〃，"00001111",”00010000〃)；ENDrompac;USEwork・rompac.ALL;ENTITYrom_memISPORT(clockresetdout)；ENDrom_mem;OUTbit;bit;bit_vector((rom_width-l)DOWNTO0)ARCHITECTUREbehavOFrommemTSSIGNALstep:integerrange0to(adrhigh-1):=0;BEGINPROCESS(reset,c

8、lock)BEGINifreset二，0’thenstep<=0;--dout<=(others=>'O');elsifclock，eventandclock」1’thenifstep=(adrhigh-1)THENstep<=adr_high-l;ELSEstep<=step+1;ENDIF;endif;ENDPROCESS;dout<=rom(step);ENDboh