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1、ReconfigurableReadback-SignalGeneratorBasedonaField-ProgrammableGateArrayJinghuanChen,JaekyunMoon,andKiaBazargan,Member,IEEEAbstract—Wehavedesignedareadback-signalgeneratortoprovidenoise-corruptedsignalstoareadchannelsimulator.ItisimplementedinaXilinxVirtex-Efield-programmablegatearray(FPGA)devi
2、ce.Thegeneratorsimulatesinhardwarethenoiseprocessesanddistortionsobservedinharddrives.Itusesembeddednonuniformrandomnumbergeneratorstosimulatetherandomcharacteristicsofvariousdisturbancesintheread/writeprocess.Thesignalgeneratorcansimulatereadbackpulses,intersymbolinterference,transitionnoise,el
3、ectronicsnoise,headandmedianonlinearity,intertrackinterference,andwritetimingerroraccordingtothecharacteristicsspecifiedbytheuser.Asampleimplementationoperatesata70-MHzclockspeed.Thedesigncaneasilybescaledfordifferenterrorrates.Thegeneratorcanbereconfiguredinrealtimetogivetheuserflexibilityandin
4、creasethecapacityoftheFPGAdevice.Thereadback-signalgeneratorcanbeintegratedintoanFPGAreadchannelsimulatororserveasatestbenchfordata-recoverycircuits.IndexTerms—Fieldprogrammablegatearray(FPGA),Gaussianpseudorandomnumbergenerator,magneticrecording,readchannel,readchannelmodeling,reconfigurablecom
5、puting,transitionnoise.I.INTRODUCTIONINTENSIVEsimulationisoftencarriedouttoinvestigateadvancedsignalprocessingtechniquesfordatastorageapplications.Thesimulationisnormallyperformedinsoftwarethatmaytakeaverylongtime.Forinstance,thesimulationofa10bit-errorrate(BER),assuming10biterrorsareobserved,ca
6、ntakedaysrunningonapersonalcomputerequippedwitha1-GHzPentiumIVprocessor.Ontheotherhand,thetargetsectorretryrates[i.e.,unrecoverableerrorratesaftererror-correction-code(ECC)]incommercialharddrivesnormallygobelow10fordesktopproductsand10forserver-classproducts.Oneapproachtospeedupthesimulationproc
7、essistoimplementthewholesimulatororpartofitinhardware.Becausethenoisecharacteristicsinharddrivesareunique,theadditivewhiteGaussiannoise(AWGN)assumption,whichiswidelyacceptedinstudyingtheperformanceofmanycommunicationsystems,
