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1、FPGA-basedsignalprocessingfortheLHCbsiliconstripdetectorsG.Haefeli,A.BayandA.GongAbstractWehavedevelopedanelectronicboard(TELL1)tointerfacetheDAQsystemoftheLHCbexperimentatCERN.Twohundredandeighty-nineTELL1boardsareneededtoreadoutthedifferentsubdetectorsincludingthesil
2、iconVEertexLOcator(VELO)(172 kstrips),theTriggerTracker(TT)(147 kstrips)andtheInnerTracker(129 kstrips).Eachboardcanhandleeither64analogor24digitalopticallinks.TheTELL1motherboardprovidescommonmodecorrection,zerosuppression,dataformatting,andalargenetworkinterfacebuffe
3、r.TosatisfythedifferentrequirementswehaveadoptedaflexibleFPGAdesignandmadeuseofmezzaninecards.MezzaninesareusedfordatainputfromdigitalopticalandanalogcopperlinksaswellasfortheGigabitEthernetinterfacetoDAQ.Keywords:LHCb;DAQ;FPGA;GigabitEthernet;Siliconstripdetectors;Com
4、monmode;Zerosuppression1.IntroductionTheLHCb[1]experimentatCERN'sLargeHadronCollider(LHC)isdedicatedtothestudiesofCPviolationandraredecaysinthe“beauty”sector.FortheDAQinterfaceanLHCbcommonreadoutboard(TELL1)hasbeendevelopedallowingtoimplementeventsynchronization,pedest
5、alsubtraction,CommonMode(CM)noisefiltering,clusterizationandnetworkinterfacing.InthefollowingwegiveanoverviewoftheLHCbDAQarchitecture,adescriptionoftheTELL1processorboardanddiscusstheprocessingrequiredfortheLHCbsiliconvertexdetector(VELO)andbythesilicontrackerdetectors
6、(TTandIT).LHCbhasthreelevelsofDAQelectronics,correspondingtothethreelevelsoftriggercalledL0,L1andHigh-LevelTrigger(HLT).TheL0electronicsisplacedclosetothedetectorandrequiresradiation-hardorradiation-tolerantcomponents.Tominimizetheamountofelectronicspronetotheradiation
7、effects,theL1electronicsisplacedbehindashieldingwall,quitefarfromtheinteractionpoint(morethan60 m).TopreservesynchronizationoverlargedistancesLHCbhasaglobalclockandfastsignaltransmissionnetwork,theTimingandFastControl(TFC)[2],implementingtheTimingandTriggerControl(TTC)
8、devicesdevelopedatCERN[3].Inparticular,aradiation-hardchip(TTCrx[4])isplacedonallfrontendelectronicstoreceivethesyste
