数字时钟(数字逻辑)课程设计报告

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1、数字时钟班级：学号：姓名：指导老师：提交日期：2011年1月8日一．系统简介：使用VHDL语言编写程序完成数字时钟的功能设计，利用软件进行编译和仿真，最后利用实验箱实现系统。二．功能简介：完成时钟的计时、调整，整点报时等基础功能，完成闹钟的设置、开启和关闭功能，整点报时的开启和关闭功能，完成日期设定和显示功能。三．总体结构逻辑框图：四．状态图：一．各模块电路图及程序：整体电路连接图：1.总控制模块：时钟脉冲分频元件：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_un

2、signed.all;entitydc4_1clkdmuxisport(clk:instd_logic;clk1,clk4,clk512:outstd_logic);enddc4_1clkdmux;architectureclkdmuxofdc4_1clkdmuxissignalc1:std_logic_vector(9downto0);beginprocess(clk)beginifclk'eventandclk='1'thenc1<=c1+1;endif;clk1<=c1(9);clk4<=c1(7);clk512<=c1(0)

3、;endprocess;endclkdmux;模式控制元件：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitydc4_2modeisport(clk4,bt_m:instd_logic;mode:outstd_logic_vector(1downto0);cr1,cr2:outstd_logic);enddc4_2mode;architecturemodeofdc4_2modeissignalmodx:std_logic_vecto

4、r(1downto0);signalc1,c2:std_logic;beginprocess(clk4,bt_m)beginifclk4'eventandclk4='1'thenifbt_m='1'thenmodx<=modx+1;c2<='1';elsec2<='0';endif;endif;ifmodx="00"thenc1<='1';elsec1<='0';endif;mode<=modx;cr1<=c1;cr2<=c2;endprocess;endmode;调节项目控制元件：libraryieee;useieee.std_l

5、ogic_1164.all;useieee.std_logic_unsigned.all;entitydc4_2modeisport(clk4,bt_m:instd_logic;mode:outstd_logic_vector(1downto0);cr1,cr2:outstd_logic);enddc4_2mode;architecturemodeofdc4_2modeissignalmodx:std_logic_vector(1downto0);signalc1,c2:std_logic;beginprocess(clk4,bt_

6、m)beginifclk4'eventandclk4='1'thenifbt_m='1'thenmodx<=modx+1;c2<='1';elsec2<='0';endif;endif;ifmodx="00"thenc1<='1';elsec1<='0';endif;mode<=modx;cr1<=c1;cr2<=c2;endprocess;endmode;数码管显示元件：libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitydc4_4

7、selisport(clk:instd_logic;sel:outstd_logic_vector(2downto0));enddc4_4sel;architectureselofdc4_4selissignalselx:std_logic_vector(2downto0);beginprocess(clk)beginifclk'eventandclk='1'thenselx<=selx+1;endif;endprocess;sel<=selx;endsel;模块波形图：1.时钟模块：时钟秒调节元件：libraryieee;usei

8、eee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitydc3_1secondisport(clk1,clk4,rest,bt_a:instd_logic;mode,se