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1、外文资料HardwareandComputerOrganizationFrom:HardwareandComputerOrganization,ArnoldS.BergerFigure6.21isanexcerptformtedatasheetforanSDRAMmemorydevicefromMicronTechnology,Inc,asemiconductormemorymanufacturerlocatedinBoise,ID.ThetimingdiagramisfortheMT48LC128MXAfamilyofSDRAMmemories.Thedevicesare513Mbitpa
2、rtsorganizedas4,8or16-bitwidedatapaths.The‘X’isaplaceholderfortheorganization(4,8or16bitwide).Thus,theMT48LC128M4A232m*isorganizedas32M*4,whiletheMT48LC128M4A2isorganizedas8M*16.ThesedevicesarefarmorecomplicatedintheiroperationthenthesimpleSRAMmemorieswe’velookedatsofar.However,wecanseethefundament
3、albrustbehaviorinFigure6.21.ThefieldsmarkedCOMMAND,ADDRESSandDQarerepresentedasbandofdata,ratherthanindividualbits.Thisisasimplificationthatallowsustoshowagroupofsignals,suchas14addressbits,withouthavingtoshowthestateofeachindividualsignal.Thebandisusedtoshowwherethesignalmustbestableandwhereitisal
4、lowedtochang.Noticehowthesignalsareallsynchronizedtotherisingedgeoftheclock.OncetheREADcommandisissuedandtheaddressisprovidedforwheretheburstistooriginate,thereisatwoclockcyclelatencyansequentiallystoreddatainthechipwillthenbeavailableoneverysuccessiveclockcycle.Clearly,thisisfarmoreefficientthenre
5、adingonebyteatatime.Whenweconsidercachememoriesingreaterdetail,we’llseethattheon-chipcachesarealsodesignedtobefilledfromexternalmemoryinburstsofdata.Thus,weincurapenaltyinhavingtoset-uptheinitialconditionsforthedatatransferfromexternalmemorytotheon-chipcaches,butoncethedatatransferparametersareload
6、ed,thememorytomemorydatatransfercantakeplacequiterapidly.Forthisfamilyofdevicesthedatatransfertakesplaceatamaximumclockrateof133MHz.NewerSDRAMdevices,calleddoubledatarate,orDDRchips,cantransferdataonboththerisingandfallingedgesoftheclock.Thus,aDDRchipwitha133MHzclockinputcantransferdataataspeedy266
7、MHZ.Thesepartsaredesignated,forreasonsunknown,,asPC2700devices.AnySDRAMchipcapableofconformingtoa266MHZclockratearePC2700.ModernDRAMdesigntakesmanydifferentforms.We’vebeendiscussingSDRAMbecausethisisthemost
