片上互连中pre-mphasis_电路的研究与设计

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1、上海交通大学硕士学位论文片上互连中pre-emphasis电路的研究与设计硕士研究生：楼媛学号：导师：毛志刚教授副导师：蒋剑飞助理研究员专业：集成电路工程所在单位：微电子学院答辩日期：2012年12月授予学位单位：上海交通大学DissertationSubmittedtoShanghaiJiaoTongUniversityfortheDegreeofMasterResearchofDriverPre-emphasisTechniquesforOn-ChipGlobalBusesCandidate：YuanLouStudentID:Supervisor

2、：Prof.ZhigangMaoAssistantSupervisor:AssistantProf.JianfeiJiangSpeciality：IntegratedCircuitEngineeringAffiliation：SchoolofMicroelectronicsDateofDefence：Dec,2012Degree-Conferring-Institution：ShanghaiJiaoTongUniversity上海交通大学硕士学位论文IIRESEARCHOFDRIVERPRE-EMPHASISTECHNIQUESFORON-CHIPB

3、USESABSTRACTWiththedevelopmentofSOCdesigns,moreandmorefunctionalityisintegratedintoasinglechip.Thecomplexityofthesystemonachipdemandsahigherrequirementofon-chipinterconnectbandwidthandreliability.Withsub-micronprocessscalingtechnology,globalinterconnectbecomesincreasinglyimport

4、antindeterminingthespeedandpowerofintegratedcircuits.Theperformanceofglobalinterconnecthasbecomethebottleneckforhigh-speeddatacommunications.Thethesismainlyfocusesonthedriverpre-emphasisarchitectureofon-chipinterconnect,whichaimstoimprovetheinterconnectchannelbandwidthandelimin

5、ateinter-symbolinterferencebyemphasizingthehigh-frequencycomponentswhileattenuatinglow-frequencyones.Theresearchworkshowedthatthedelayinpre-emphasiscircuitstructurehasasignificantimpactoncircuitperformance.Laplacetransformwasappliedtoanalyzethefrequencyresponsecurve,thusobtaini

6、ngtheoptimaldelayforcircuitperformance.Thesimulatingenvironmentisaninterconnectwiththelengthof10mmunder90nmprocess.Experimentalresultsshowedabetterperformancewhenapplyingouroptimaldelayparameter.Specifically,theunder10-10partofBERforoutputsignalwas38.9%forconventionalwireand56.

7、3%forcapacitivelydrivenwire.Therefore,theoptimizedpre-emphasiscircuitcouldeffectivelyimprovethetransmissionbandwidth.KEYWORDS:pre-emphasis,drivercircuit,highspeedinterconnect,on-chip上海交通大学硕士学位论文III目录第一章绪论··········································································

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