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1、ENTITYmux21ISPORT(A,B,S:INBIT;Y:OUTBIT);ENDENTITYmux21;ARCHITECTUREoneOFmux21ISBEGINY<=AWHENS='0'ELSEB;ENDARCHITECTUREone;ENTITYxor2ISport(a,b:inbit;c:outBIT);endentityxor2;ARCHITECTUREoneOFxor2ISbeginc<='0'whena=belse'1';endARCHITECTUREone;ENTITYmux41ISPORT(A,B,C,D,S1,S2:INBIT;Y:OUTBIT);ENDENTI
2、TYmux41;ARCHITECTUREonsOFmux41ISCOMPONENTmux21PORT(A,B,S:INBIT;Y:OUTBIT);ENDCOMPONENT;COMPONENTxor2port(a,b:inbit;c:outbit);ENDCOMPONENT;SIGNALd1,e,f:bit;BEGINu1:mux21PORTMAP(A=>A,B=>B,S=>S1,Y=>e);u2:mux21PORTMAP(A=>C,B=>D,S=>S2,Y=>f);u3:xor2PORTMAP(a=>S1,b=>S2,c=>d1);u4:mux21PORTMAP(A=>e,B=>f,S
3、=>d1,Y=>Y);ENDARCHITECTUREons;（四选一）LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYh_adderISPORT(A,B:INSTD_LOGIC;CO,SO:OUTSTD_LOGIC);ENDENTITYh_adder;ARCHITECTUREfh1OFh_adderISBEGINSO<=NOT(AXOR(NOTB));CO<=AANDB;ENDARCHITECTUREfh1;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYor2aISPORT(a,b:INSTD_LOG
4、IC;c:OUTSTD_LOGIC);ENDENTITYor2a;ARCHITECTUREoneOFor2aISBEGINc<=aORb;ENDARCHITECTUREone;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYf_adderISPORT(ain,bin,cin:INSTD_LOGIC;cout,sum:OUTSTD_LOGIC);ENDENTITYf_adder;ARCHITECTUREfd1OFf_adderISCOMPONENTh_adderPORT(A,B:INSTD_LOGIC;CO,SO:OUTSTD_LOGIC);EN
5、DCOMPONENT;COMPONENTor2aPORT(a,b:INSTD_LOGIC;c:OUTSTD_LOGIC);ENDCOMPONENT;SIGNALd,e,f:STD_LOGIC;BEGINu1:h_adderPORTMAP(A=>ain,B=>bin,CO=>d,SO=>e);u2:h_adderPORTMAP(A=>e,B=>cin,CO=>f,SO=>sum);u3:or2aPORTMAP(a=>d,b=>f,c=>cout);ENDARCHITECTUREfd1;LIBRARYIEEE;（一位全加器）
