基于vhdl 的 数字钟的设计

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1、顶层文件-----------------------------------------------------------------------------------Company:--Engineer:----CreateDate:09:40:4701/14/2014--DesignName:--ModuleName:digital_clock-Behavioral--ProjectName:--TargetDevices:--Toolversions:--Description:----Dependencies:----

2、Revision:--Revision0.01-FileCreated--AdditionalComments:------------------------------------------------------------------------------------libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;--Uncommentthefollowinglibraryd

3、eclarationifusing--arithmeticfunctionswithSignedorUnsignedvalues--useIEEE.NUMERIC_STD.ALL;--Uncommentthefollowinglibrarydeclarationifinstantiating--anyXilinxprimitivesinthiscode.--libraryUNISIM;--useUNISIM.VComponents.all;ENTITYdigital_clockISPORT(setup:INSTD_LOGIC;--预

4、置脉冲手动set:INSTD_LOGIC;----upd0选择工作模式clk:INSTD_LOGIC;----输入1Khz脉冲需要经过1000分频产生1hz脉冲tn:INSTD_LOGIC;----相当于题目要求中的up为高时预置+1为低时-1en:INSTD_LOGIC;-----使能H_Year:OUTSTD_LOGIC_VECTOR(3DOWNTO0);H_Year1:OUTSTD_LOGIC_VECTOR(3DOWNTO0);M_Mon:OUTSTD_LOGIC_VECTOR(3DOWNTO0);M_Mon1:OUTSTD_

5、LOGIC_VECTOR(3DOWNTO0);S_Day:OUTSTD_LOGIC_VECTOR(3DOWNTO0);S_Day1:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDdigital_clock;ARCHITECTUREbdf_typeOFdigital_clockISCOMPONENTdaymony1PORT(clk0:INSTD_LOGIC;en:INSTD_LOGIC;lock:INSTD_LOGIC_VECTOR(2DOWNTO0);da0:OUTSTD_LOGIC_VECTOR(3DOWNT

6、O0);da1:OUTSTD_LOGIC_VECTOR(3DOWNTO0);mo0:OUTSTD_LOGIC_VECTOR(3DOWNTO0);mo1:OUTSTD_LOGIC_VECTOR(3DOWNTO0);ya0:OUTSTD_LOGIC_VECTOR(3DOWNTO0);ya1:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDCOMPONENT;COMPONENTfenpinPORT(upd0:INSTD_LOGIC;---外接顶层setclk:INSTD_LOGIC;---外接顶层f10f_clk:OU

7、TSTD_LOGIC;-----分频输出为1hzlock:OUTSTD_LOGIC_VECTOR(2DOWNTO0)---计数set脉冲000-111循环产生工作模式);ENDCOMPONENT;COMPONENTs_m_hourPORT(clk0:INSTD_LOGIC;en:INSTD_LOGIC;lock:INSTD_LOGIC_VECTOR(2DOWNTO0);co:OUTSTD_LOGIC;h0:OUTSTD_LOGIC_VECTOR(3DOWNTO0);h1:OUTSTD_LOGIC_VECTOR(3DOWNTO0);m

8、0:OUTSTD_LOGIC_VECTOR(3DOWNTO0);m1:OUTSTD_LOGIC_VECTOR(3DOWNTO0);s0:OUTSTD_LOGIC_VECTOR(3DOWNTO0);s1:OUTSTD_LOGIC_VEC