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时间:2021-04-01
《数字电路英文版-第十二单元.ppt》由会员上传分享,免费在线阅读,更多相关内容在教育资源-天天文库。
1、CHAPTER12MEMORYANDSTORAGE§12.1BASICSOFSEMICONDUCTORMEMORYMemoryistheportionofasystemforstoringbinarydatainlargequantities.Semiconductormemoriesconsistofarraysofstorageelementsthatareeitherlatchesorcapacitors.2UnitsofBinaryData:Bits,Bytes,Nibbles,andWords184n*8
2、(9)3TheBasicSemiconductorMemoryArray4112348765623487512346515234113141234656462631(a)8*8array(b)16*4array(c)64*1array165MemoryAddressandCapacity1123487651234875(b)Theaddressofthebytehighlightedinblueisrow3.1123487651234875(a)Theaddressofthebithighlightedinblue
3、isrow5,column4.BasicMemoryoperationsAddressdecoderMemoryarrayAddressbusDatabusReadWrite67BasicMemoryoperationsAddressdecoder①Write00123456711111101111100111111111111100000000000000000000000000000010000111DatabusAddressbus10110001101AddressregisterDataregister③
4、②TheWriteOperation8Addressdecoder①Read001234567111110111110011111111111100000000000000000000000000000010000111Addressbus01111000001Addressregister③②TheReadOperationDatabusDataregister9§12.2RANDOM-ACCESSMEMORIES(RAMs)RAMsarereal/writememoriesinwhichdatacanbewri
5、ttenintoorreadfromanyselectedaddressinanysequence.ARAMistypicallyusedforshort-termdatastoragebecauseitcannotretainstoreddatawhenpoweristurnoff.10StaticRAMs(SRAMs)DataDataBitSelect+Vcc11DataI/OBit0DataI/OBit3DataI/OBit2DataI/OBit1DataInput/OutputBuffersandContr
6、olRowSelectnRowSelect2RowSelect1RowSelect012Memoryarray256rowsx128X8columns256rows128columns8bits13Memoryarray256rowsx128x8columnsRowdecoderColumnI/OColumndecoderInputdatacontrolAddresslinesAddresslinesI/O1I/O8CSWEOEG1G2OutputdataTheBurstFeatureSynchronousSRAM
7、snormallyhaveanaddressburstfeature,whichallowsthememorytoreadorwriteatuptofourlocationsusingasingleaddress.BurstLogicBurstcontrolBinarycounterQ1Q0CLKA0A1A0’A1’LSBsofexternaladdressLSBsofinternalburstaddress14CacheMemory:Cachememoryisarelativelysmall,high-speed
8、memorythatstoresthemostrecentlyusedinstructionsordatafromthelargerbutslowermainmemory.CacheAnalogy:refrigerator(cache)supermarket15Micro-processorL1cache(internal)CachecontrollerL2
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