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ID:55209926
大小:23.00 KB
页数:8页
时间:2020-05-03
《VHDL-4位计数器的设计.doc》由会员上传分享,免费在线阅读,更多相关内容在教育资源-天天文库。
1、*******bcd译码器******libraryieee;useieee.std_logic_1164.all;entitydecoderisport(bcd:instd_logic_vector(3downto0);y:outstd_logic_vector(7downto0));endentity;architecturertlofdecoderisbeginprocess(bcd)begincasebcdiswhen"0000"=>y<="";--0:hgfedcbawhen"0001"=>y<="";--1when"0
2、010"=>y<="";--2when"0011"=>y<="";--3when"0100"=>y<="";--4when"0101"=>y<="";--5when"0110"=>y<="";--6when"0111"=>y<="";--7when"1000"=>y<="";--8when"1001"=>y<="";--9whenothers=>y<="";endcase;endprocess;endrtl;***********多路选择控制************libraryieee;useieee.std_logic_116
3、4.all;entitymuxisport(input_a:instd_logic_vector(3downto0);input_b:instd_logic_vector(3downto0);input_c:instd_logic_vector(3downto0);input_d:instd_logic_vector(3downto0);sel:instd_logic_vector(1downto0);y:outstd_logic_vector(3downto0));endentitymux;architecturertlofmu
4、xisbeginprocess(sel)isbeginif(sel="00")theny<=input_a;elsif(sel="01")theny<=input_b;elsif(sel="10")theny<=input_c;elsey<=input_d;endif;endprocess;endrtl;************分频************libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityclk4msisport(
5、clk:instd_logic;y:bufferstd_logic);endentityclk4ms;architecturertlofclk4msissignala:STD_LOGIC_VECTOR(17DOWNTO0);beginprocess(clk)isbeginif(clk'eventandclk='1')thenif(a="")thena<="";y<=noty;elsea<=a+'1';endif;endif;endprocess;endrtl;************计数器************libraryie
6、ee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitycntisport(clk,clr,en:instd_logic;a:outstd_logic_vector(3downto0);b:outstd_logic_vector(3downto0);c:outstd_logic_vector(3downto0);d:outstd_logic_vector(3downto0));endentitycnt;architecturertlofcntissign
7、aldout_0,dout_10,dout_100,dout_1000:std_logic_vector(3downto0);beginprocess(clr,clk,en)isbegina<=dout_0;b<=dout_10;c<=dout_100;d<=dout_1000;ifclr='1'thendout_0<="0000";dout_10<="0000";dout_100<="0000";dout_1000<="0000";elsif(en='1')thenif(clk'eventandclk='1')thenif(do
8、ut_0="1001")then---计数dout_0<="0000";elsedout_0<=dout_0+'1';endif;elsif(clk'eventandclk='1'anddout_0="1001")thenif(dout_10="1
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