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时间:2019-03-13
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1、ApplicationNote:TestBenchesRWritingEfficientTestbenchesAuthor:MujtabaHamidXAPP199(v1.0)June11,2001SummaryThisapplicationnoteiswrittenforlogicdesignerswhoarenewtoHDLverificationflows,andwhodonothaveextensivetestbench-writingexperience.TestbenchesaretheprimarymeansofverifyingHD
2、Ldesigns.Thisapplicationnoteprovidesguidelinesforlayingoutandconstructingefficienttestbenches.Italsoprovidesanalgorithmtodevelopaself-checkingtestbenchforanydesign.AlldesignfilesforthisapplicationnoteareavailableontheFTPsiteat:PC:ftp://ftp.xilinx.com/pub/applications/xapp/xap
3、p199.zipUNIX:ftp://ftp.xilinx.com/pub/applications/xapp/xapp199.tar.gzIntroductionDuetoincreasesindesignsizeandcomplexity,digitaldesignverificationhasbecomeanincreasinglydifficultandlaborioustask.Tomeetthischallenge,verificationengineersrelyonseveralverificationtoolsandmethod
4、s.Forlarge,multi-milliongatedesigns,engineerstypicallyuseasuiteofformalverificationtools.However,forsmallerdesigns,designengineersusuallyfindthatHDLsimulatorswithtestbenchesworkbest.TestbencheshavebecomethestandardmethodtoverifyHLL(High-LevelLanguage)designs.Typically,testben
5、chesperformthefollowingtasks:•Instantiatethedesignundertest(DUT)•StimulatetheDUTbyapplyingtestvectorstothemodel•Outputresultstoaterminalorwaveformwindowforvisualinspection•OptionallycompareactualresultstoexpectedresultsTypically,testbenchesarewrittenintheindustry-standardVHDL
6、orVeriloghardwaredescriptionlanguages.Testbenchesinvokethefunctionaldesign,thenstimulateit.Complextestbenchesperformadditionalfunctions—forexample,theycontainlogictodeterminetheproperdesignstimulusforthedesignortocompareactualtoexpectedresults.Theremainingsectionsofthisnotede
7、scribethestructureofawell-composedtestbench,andprovideanexampleofaself-checkingtestbench—onethatautomatesthecomparisonofactualtoexpectedtestbenchresults.Figure1showsastandardHDLverificationflowwhichfollowsthestepsoutlinedabove.SincetestbenchesarewritteninVHDLorVerilog,testben
8、chverificationflowscanbeportedacrossplatformsandvendortools.Also,sin
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