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1、ANovelUltra-FastHeuristicforVLSICADSteinerTreesBharatKrishnaC.Y.RogerChenNareshK.SehgalIntelCorporationSyracuseUniversityIntelCorporation2200MissionCollegeBlvd.Dept.ofElec.&Comp.Engineering2200MissionCollegeBlvd.SantaClara,CA95052Syracuse,NY13244SantaClar
2、a,CA95052bharat.krishna@intel.comcrchen@syr.edunaresh.k.sehgal@intel.comABSTRACTestimateofthewirelengthforanet,theirslowruntimemakesthemun-usableformanyapplications.SomeInallstagesofVLSIchipdesign,routingestimationisapplicationsusehalfperimeter[2]astheest
3、imationofnetrequiredtoaccountfortheeffectofinterconnects.Welengths,whichisafastbutinaccuratemethodwhentheproposeafastSteinertreeconstructionalgorithm,whichisnumberofpointstobeconnectedismorethan3.Inthis3-180timesfasterfor10-300pointSteinertrees,andwithinp
4、aper,wepresenttwovariationsofanovelalgorithm.One2.5%ofthelengthoftheBatched-1-Steinertree.Theoptionofthealgorithmhasaruntimethatisupto180Xproposedmethodcanbeusedasafastnetlengthestimationfasterandthetreelengthis2.5%morethantheBatched-1-toolinVLSICADapplic
5、ations,e.g.intheinnercycleofaSteineralgorithm[4].Thesecondvariationhasafasterfloorplanning/placementengine.runtime(250X),butthetreelengthis4%more.Inrealcircuits,itiscommontohaveabout5%ofthenetshavingatCategories&SubjectDescriptorsleast10nodes.Ourmethodcan
6、beusedtoquicklyandmoreB.7.2[IntegratedCircuits]:DesignAids-Layout,Placementandaccuratelyestimatethewirelengthofthesenets.Routing.2.RELATEDWORKGeneralTerms:AlgorithmsTherehasbeenextensiveresearchandpublishedwork[3][4][5][6][9][10][11]ongeneratingminimumlen
7、gthKeywords:Steinertrees,Routing,InterconnectestimationSteinertrees.ASteinertreeisarectilineartreeforagivensetofverticesandsomeadditionalverticestocreatetheminimumlengthspanningtree.Theseadditionalverticesare1.INTRODUCTIONknownas“Steinerpoints”.InVLSIinte
8、gratedcircuits,electricallyequivalentpointsareVariousgraph-basedmethods[3][4][5][6][9]havebeenusuallyconnectedbyroutingthewiresinManhattanproposedtofindtheSteinerpoints.Theyallusetheearliergeometries,i.e.thewiresare
