eda考试所有程序参考

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1、1.Genericdecode匚libraryieee;useieee.std_logic_l164.all;entitysisgeneric(n:integer:=8);port(sel:inintegerrange0ton-1;ena:instd_logic;x:outsld」ogic_vector(n-ldownto0));ends;architecturesofsisbeginprocess(ena,sel)variablet2:std_logic_vector(x°highdownto0);begint2:=(others=>,r);if(ena-1')thent

2、2(sel):='0,;endif;x<=t2;endprocess;ends;2.Genericparitydetector.libraryieee;useieee.std_logic_l164.all;entitysisgeneric(n:integer:=8);poil(input:instd_logic_vector(ndownto0);output:outstdjogic);ends;architecturesofsisbeginprocess(input)variablet:std_logic;beginforiininputrangeloopt:=txorin

3、put(i);endloop;output<=t;endprocess;ends;3.Genericparitygeneratorlibraryieee;useieee.std_logic_l164.all;entitysisgeneric(n:integer:=8);poil(input:instd_logic_vector(downto0);output:outstd_logic_vector(ndownto0));ends;architecturesofsisbeginprocess(input)variablet:std_logic;variabletl:std_l

4、ogic_vector(outpufhighdownto0)begint=0‘；foriininputrangeloopt:=txorinput(i);tl:=t&inpul;endloop;output<=tl;endprocess;ends;4.Simplemultiplexer.libraryieee;useieee.std」ogic_l164.all;entitysisport(a,b,c,d:instd」ogic;s:instd_logic_vector(1downto0);y:outstd_logic);ends;architecturesofsisbeginw

5、ithsselecty<=awhen"00",bwhen“01",cwhenTO”，dwhenothers;ends;5.带q和qbar的DFF.libraryieee;useieee.std_logic_l164.all;entitysisport(d,clk:instd」ogic;q:bufferstd」ogic;qbar:outstd_logic);ends;architecturesofsiSbeginprocess(clk)beginif(clkeventandelk-T)thenqv二d;endif;endprocess;qbar<=notq;ends;5.Tr

6、i-statebuffe匚libraryieee;useieee.std_logic_l164.all;entitysisport(input:INstd_logic_vector(7downto0);ena:INstdjogic;output:outstd_logic_vector(7downto()));ends;architecturesofsisbeginoutput<=inputwhen(ena=,0,)else”ZZZZZZZZ";ends;6.Adder.libraryieee;useieee.std」ogic_l164.all;useieee.std_log

7、ic_arith.all;entitysisport(cint:instd」ogic;a,b:inunsigned(7downto0);cout:outstdjogic;sum:outunsigned(7downto0));ends;architecturesofsissignallajbjsjc:unsigned(8downto0);beginla<=,0&a;lb<='0&b;lc<=n00000000n&cint;ls<=la+lb+lc;sum<=ls(7downto0);cout<=ls(8);ends;