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1、一个可以综合的Verilog写的FIFO存储器SynthesizableFIFOModelThisexampledescribesasynthesizableimplementationofaFIFO.TheFIFOdepthandFIFOwidthinbitscanbemodifiedbysimplychangingthevalueoftwoparameters,`FWIDTHand`FDEPTH.Forthisexample,theFIFOdepthis4andtheFIFOwidthis32b
2、its.Theinput/outputportsoftheFIFOareshowninFigureF-1.FigureF-1.FIFOInput/OutputPortsInputportsAllportswithasuffix"N"arelow-asserted.Clk—ClocksignalRstN—ResetsignalData_In—32-bitdataintotheFIFOFInN—WriteintoFIFOsignalFClrN—ClearsignaltoFIFOFOutN—Readfro
3、mFIFOsignalOutputportsF_Data—32-bitoutputdatafromFIFOF_FullN—SignalindicatingthatFIFOisfullF_EmptyN—SignalindicatingthatFIFOisemptyF_LastN—SignalindicatingthatFIFOhasspaceforonedatavalue-6-F_SLastN—SignalindicatingthatFIFOhasspacefortwodatavaluesF_Firs
4、tN—SignalindicatingthatthereisonlyonedatavalueinFIFO TheVerilogHDLcodefortheFIFOimplementationisshowninExampleF-1.ExampleF-1SynthesizableFIFOModel//////////////////////////////////////////////////////////////////////FileName:"Fifo.v"//Author:VenkataRam
5、anaKalapatapu//Company:SandMicroelectronicsInc.//(nowapartofSynopsys,Inc.),//Profile:SanddevelopsSimulationModels,SynthesizableCoresand//PerformanceAnalysisToolsforProcessors,busesand//memoryproducts.Sand'sproductsincludemodelsfor//industry-standardcom
6、ponentsandcustom-developedmodels//forspecificsimulationenvironments.////////////////////////////////////////////////////////////////////`defineFWIDTH32//WidthoftheFIFO.`defineFDEPTH4//DepthoftheFIFO.`defineFCWIDTH2//CounterWidthoftheFIFO2topower//FCWID
7、TH=FDEPTH.moduleFIFO(Clk,RstN,Data_In,FClrN,FInN,FOutN,F_Data,F_FullN,F_LastN,F_SLastN,F_FirstN,F_EmptyN);inputClk;//CLKsignal.inputRstN;//LowAssertedResetsignal.input[(`FWIDTH-1):0]Data_In;//DataintoFIFO.inputFInN;//WriteintoFIFOSignal.inputFClrN;//Cl
8、earsignaltoFIFO.inputFOutN;//ReadfromFIFOsignal.output[(`FWIDTH-1):0]F_Data;//FIFOdataout.outputF_FullN;//FIFOfullindicatingsignal.outputF_EmptyN;//FIFOemptyindicatingsignal.-6-outputF_LastN;//FIFOLastbutonesignal.outputF_SLastN;//FIFOS
