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ID:15421566
大小:62.50 KB
页数:6页
时间:2018-08-03
《一个可以综合的verilog 写的fifo存储器》由会员上传分享,免费在线阅读,更多相关内容在行业资料-天天文库。
1、一个可以综合的Verilog写的FIFO存储器SynthesizableFIFOModelThisexampledescribesasynthesizableimplementationofaFIFO.TheFIFOdepthandFIFOwidthinbitscanbemodifiedbysimplychangingthevalueoftwoparameters,`FWIDTHand`FDEPTH.Forthisexample,theFIFOdepthis4andtheFIFOwidthis32bits.Theinput/outputportsoftheFIF
2、OareshowninFigureF-1.FigureF-1.FIFOInput/OutputPortsInputportsAllportswithasuffix"N"arelow-asserted.Clk—ClocksignalRstN—ResetsignalData_In—32-bitdataintotheFIFOFInN—WriteintoFIFOsignalFClrN—ClearsignaltoFIFOFOutN—ReadfromFIFOsignalOutputportsF_Data—32-bitoutputdatafromFIFOF_FullN—Sig
3、nalindicatingthatFIFOisfullF_EmptyN—SignalindicatingthatFIFOisemptyF_LastN—SignalindicatingthatFIFOhasspaceforonedatavalue-6-F_SLastN—SignalindicatingthatFIFOhasspacefortwodatavaluesF_FirstN—SignalindicatingthatthereisonlyonedatavalueinFIFO TheVerilogHDLcodefortheFIFOimplementationis
4、showninExampleF-1.ExampleF-1SynthesizableFIFOModel//////////////////////////////////////////////////////////////////////FileName:"Fifo.v"//Author:VenkataRamanaKalapatapu//Company:SandMicroelectronicsInc.//(nowapartofSynopsys,Inc.),//Profile:SanddevelopsSimulationModels,SynthesizableC
5、oresand//PerformanceAnalysisToolsforProcessors,busesand//memoryproducts.Sand'sproductsincludemodelsfor//industry-standardcomponentsandcustom-developedmodels//forspecificsimulationenvironments.////////////////////////////////////////////////////////////////////`defineFWIDTH32//Widthof
6、theFIFO.`defineFDEPTH4//DepthoftheFIFO.`defineFCWIDTH2//CounterWidthoftheFIFO2topower//FCWIDTH=FDEPTH.moduleFIFO(Clk,RstN,Data_In,FClrN,FInN,FOutN,F_Data,F_FullN,F_LastN,F_SLastN,F_FirstN,F_EmptyN);inputClk;//CLKsignal.inputRstN;//LowAssertedResetsignal.input[(`FWIDTH-1):0]Data_In;//
7、DataintoFIFO.inputFInN;//WriteintoFIFOSignal.inputFClrN;//ClearsignaltoFIFO.inputFOutN;//ReadfromFIFOsignal.output[(`FWIDTH-1):0]F_Data;//FIFOdataout.outputF_FullN;//FIFOfullindicatingsignal.outputF_EmptyN;//FIFOemptyindicatingsignal.-6-outputF_LastN;//FIFOLastbutonesignal.outputF_SL
8、astN;//FIFOS
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