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1、1240IEEEJOURNALOFSOLID-STATECIRCUITS,VOL.42,NO.6,JUNE2007A21-GHz8-ModulusPrescaleranda20-GHzPhase-LockedLoopFabricatedin130-nmCMOSYanpingDing,StudentMember,IEEE,andKennethK.O,SeniorMember,IEEEAbstract—A1.5-V256-2638-modulusprescaleranda1.5-VIntermsofPLLswhoseout
2、putfrequenciescanbecontrolled,integer-Nphase-lockedloop(PLL)witheightdifferentoutputnoneoperatingat20-GHzfrequencyhavebeenreported.Afrequencieshavebeenimplementedina0.13-mfoundryCMOSfractional-NPLLfabricatedin130-nmCMOSachievestheprocess.Thesynchronousdivide-by-
3、4/5circuitusescurrentmodehighestoperatingfrequencyof13GHz[7].Inthisdesign,alogic(CML)D-flip-flopswithresistiveloadstoachieve21-GHzmaximumoperatingfrequencyatinputpowerof0dBm.Thephase-selectingmultimodulusprescalerhasbeenused.Thedividerisusedtoimplementan8-modulusp
4、rescalerconsumingwholePLLconsumes60mWofpowerwhiletheprescaler6-mAcurrentand9-mWpower.Thisextremelylowpowerconsumes40mW.ACMLdual-modulusprescalerwithanconsumptionisachievedbyradicallydecreasingthesizesofextrafeedbacknetworkhasbeenreportedin[8].Thefeedbacktransist
5、orsinthedivider.Utilizingtheprescaler,acharge-pumpnetworksincreasetheoperatingfrequencyoftheprescalerinteger-NPLLhasbeendemonstratedwith20-GHzoutputfre-quency.Thein-bandphasenoiseofthePLLat60-kHzoffsetandto14GHz.Utilizingthisprescaler,a10.4-GHzPLLwasout-of-bandp
6、hasenoiseat10-MHzoffsetare80dBc/Hzanddemonstratedina0.18-mCMOStechnology.Theoperating116.1dBc/Hz,respectively.Thelockingrangeisfrom20.05tofrequenciesofthesePLLsaresubstantiallylowerthanthose21GHz.ThePLLconsumes15-mAcurrentand22.5-mWpowerwithafixeddivideratio.This
7、isprimarilyduetothelowerfroma1.5-Vpowersupply.maximumoperatingfrequencyofmultimodulusprescalers.IndexTerms—CMOS,dual-modulusprescaler,integer-Nphase-Thispaperpresentsalow-power21-GHz8-moduluslockedloop(PLL),lowpower,multimodulusprescaler.prescaleranditsapplicati
8、onina20-GHzinteger-NPLLthatcanbeusedinadual-conversiontransceiverforoperationinthe24-GHzISMband.ThisPLLcanbeusedinadual-con-I.INTRODUCTIONversionradiorequiringasingle