数字时钟数电设计

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1、--数字电路课程设计VHDL语言数字钟-word.zl--一、系统功能概述1.完成秒／分／时的依次显示并正确计数；2.秒/分／时各段个位满10正确进位，秒／分能做到满60向前进位；3.定时闹钟：实现整点报时，又扬声器发出报时声音；4.时间设置即手动调时功能，能对不准确的时间进展分/时的调整。二、系统组成以及系统各局部的设计1、顶层文件2、系统以及各个模块的仿真波形1)分频模块〔原理图输入〕-word.zl--1)秒模块程序libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.

2、all;entitySECONDisport(clk,clr:instd_logic;----时钟/清零信号sec1,sec0:outstd_logic_vector(3downto0);----秒高位/低位co:outstd_logic);-------输出/进位信号endSECOND;architectureSECofSECONDisbeginprocess(clk,clr)variablet1,t0:std_logic_vector(3downto0);---计数beginifclr='1'then----当ckr为1时，上下位均为0t1:="0

3、000";t0:="0000";elsifclk'eventandclk='1'thenift1="0101"andt0="1000"then----当记数为58〔实际是经过59个记时脉冲〕co<='1';----进位t0:="1001";----低位为9elsift0<"1001"then----小于9时t0:=t0+1;----计数elset0:="0000";ift1<"0101"then----高位小于5时t1:=t1+1;elset1:="0000";co<='0';endif;endif;endif;sec1<=t1;sec0<=t0;en

4、dprocess;endSEC;-word.zl--3〕分模块程序libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityMINUTEisport(clk,en:instd_logic;min1,min0:outstd_logic_vector(3downto0);co:outstd_logic);endMINUTE;architectureMINofMINUTEisbeginifclk'eventandclk='1'thenifen='1'thenift1

5、="0101"andt0="1000"thenco<='1';t0:="1001";elsift0<"1001"thent0:=t0+1;elset0:="0000";ndMINUTE;architectureMINofMINUTEisbeginift1<"0101"thent1:=t1+1;elset1:="0000";co<='0';endif;endif;endif;endif;min1<=t1;min0<=t0;endprocess;endMIN;-word.zl--4〕时模块程序libraryieee;useieee.std_logic_11

6、64.all;useieee.std_logic_unsigned.all;entityHOURisport(clk,en:instd_logic;----输入时钟/高电平有效的使能信号h1,h0:outstd_logic_vector(3downto0));----时高位/低位endHOUR;architecturehour_arcofHOURisbeginprocess(clk)variablet1,t0:std_logic_vector(3downto0);----记数beginifclk'eventandclk='1'then---上升沿触发i

7、fen='1'then---同时“使能〞为1ift1="0010"andt0="0011"thent1:="0000";----高位/低位同时为0时t0:="0000";elsift0<"1001"then----低位小于9时，低位记数累加t0:=t0+1;elset0:="0000";t1:=t1+1;-----高位记数累加endif;endif;endif;h1<=t1;h0<=t0;endprocess;endhour_arc;-word.zl--5〕动态扫描模块libraryieee;useieee.std_logic_1164.all;use

8、ieee.std_logic_unsigned.all;useieee.std_logic_a