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1、第四章组合逻辑电路设计多任务器与解任务器译码器与编码器比较器数码转换算术运算只读存储器三态与双向界面设计3－8译码器A0A1A2ENY0Y1Y2Y3Y4Y5Y6Y7A0A1A2ENY0Y1Y2Y3Y4Y5Y6Y70001001101010111100110111101111110000000010000000010000000010000000010000000010000000010000000011.译码器与编码器3－8译码器8－3编码器传输线或网络Y0Y1Y2Y3Y4Y5Y6Y7A0A1A210000000010000000010000000
2、01000000001000000001000000001000000001000001010011100101110111LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYCH4_1_1ISPORT(A:INSTD_LOGIC_VECTOR(2DOWNTO0);EN:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(7DOWNTO0));ENDCH4_1_1;ARCHITECTUREDEC_BEHAVEOFCH4_1_1ISSIGNALSEL:STD_LOGIC_VECTOR(3DOWNT
3、O0);BEGINSEL(0)<=EN;SEL(1)<=A(0);SEL(2)<=A(1);SEL(3)<=A(2);WITHSELSELECTY<="00000001"WHEN"0001","00000010"WHEN"0011","00000100"WHEN"0101","00001000"WHEN"0111","00010000"WHEN"1001","00100000"WHEN"1011","01000000"WHEN"1101","10000000"WHEN"1111","11111111"WHENOTHERS;ENDDEC_BEHAVE
4、;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYCH4_1_2ISPORT(A:INSTD_LOGIC_VECTOR(7DOWNTO0);EN:INSTD_LOGIC;Y:OUTSTD_LOGIC_VECTOR(2DOWNTO0));ENDCH4_1_2;ARCHITECTUREENDEC_BEHAVEOFCH4_1_2ISSIGNALSEL:STD_LOGIC_VECTOR(8DOWNTO0);BEGINSEL<=EN&A;WITHSELSELECTY<="000"WHEN"100000001","00
5、1"WHEN"100000010","010"WHEN"100000100","011"WHEN"100001000","100"WHEN"100010000","101"WHEN"100100000","110"WHEN"101000000","111"WHEN"110000000","000"WHENOTHERS;ENDENDEC_BEHAVE;LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;ENTITYCH4_1_2ISPORT(A:INSTD_LOGIC_VECTOR(7DOWNTO0);EN:INSTD_LO
6、GIC;Y:OUTSTD_LOGIC_VECTOR(2DOWNTO0));ENDCH4_1_2;ARCHITECTUREENDECOFCH4_1_2ISBEGINY(2)<=(A(7)ORA(6)ORA(5)ORA(4))ANDEN;Y(1)<=(A(7)ORA(6)ORA(3)ORA(2))ANDEN;Y(0)<=(A(7)ORA(5)ORA(3)ORA(1))ANDEN;ENDENDEC;2.多任务器与解多任务器ABCDS0S1Z地址选择线输出S0S1Z00110101ABCDY(0)Y(1)Y(2)Y(3)S0S1IN地址选择线输出S0S1Y
7、00110101Y(0)Y(1)Y(2)Y(3)LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;USEIEEE.STD_LOGIC_ARITH.ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;ENTITYch4_2_1ISPORT(A,B,C,D:INSTD_LOGIC_VECTOR(3DOWNTO0);S:INSTD_LOGIC_VECTOR(1DOWNTO0);Z:OUTSTD_LOGIC_VECTOR(3DOWNTO0));ENDch4_2_1;ARCHITECTURECONC_BEHAVE
8、OFch4_2_1ISBEGINZ<=AWHENS="00"ELSEBWHENS="01"ELSECWHENS="10"E
