哈工大CPU设计代码.docx

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1、五.详细代码1CPU例化libraryIEEE;useIEEE.STD_LOGIC_1164.ALL;useIEEE.STD_LOGIC_ARITH.ALL;useIEEE.STD_LOGIC_UNSIGNED.ALL;----Uncommentthefollowinglibrarydeclarationifinstantiating----anyXilinxprimitivesinthiscode.libraryUNISIM;--useUNISIM.VComponents.all;entityCPUisport(CLK:instd_logic;RST:instd

2、_logic;DBUS:inoutstd_logic_vector(15downto0);ABUS:outstd_logic_vector(15downto0);nMREQ:outstd_logic;--片选nRD:outstd_logic;--读信号nWR:outstd_logic;--写信号nBHE:outstd_logic;--高位访问允许nBLE:outstd_logic;--低位访问允许abus_data:outstd_logic_vector(15downto0);dbus_data:outstd_logic_vector(15downto0);cs_

3、data:outstd_logic;wr_data:outstd_logic;rd_data:outstd_logic;bh_data:outstd_logic;bl_data:outstd_logic;beat:outstd_logic_vector(3downto0);ir:outstd_logic_vector(15downto0);cy_out:outstd_logic;z_out:outstd_logic);endCPU;architectureBehavioralofCPUiscomponentjiepaiisPort(clk:inSTD_LOGIC;

4、rst:inSTD_LOGIC;k:outSTD_LOGIC_VECTOR(3downto0));endcomponent;componentquzhiisPort(rst:instd_logic;--复位k0,k1:instd_logic;--时钟控制pc_in_flag:instd_logic;--PC回写允许ir_in:instd_logic_vector(15downto0);--IR进入pc_in:instd_logic_vector(15downto0);--PC回写visit_mem_flag:outstd_logic;--访存信号pc_out:ou

5、tstd_logic_vector(15downto0);--PC输出ir_out:outstd_logic_vector(15downto0)--IR输出);endcomponent;componentyunsuanisPort(rst:instd_logic;--复位信号k0,k1,k2,k3:instd_logic;--节拍控制rewrite_flag:instd_logic;--寄存器回写允许rewrite_data:instd_logic_vector(7downto0);--寄存器回写数据ir_in:instd_logic_vector(15downt

6、o0);--指令IR进入aluout:inoutstd_logic_vector(7downto0);--运算结果输出addr:outstd_logic_vector(15downto0);--准备好的地址输出if_reg:outstd_logic;--是否回写寄存器if_pc:outstd_logic;--是否回写pcm_r:outstd_logic;--给存储器管理模块读信号m_w:outstd_logic;--给存储器管理模块写信号CyFlag:outstd_logic;ZFlag:outstd_logic;toHX:outstd_logic_vector(

7、15downto0));endcomponent;componentcunchuisPort(rst:instd_logic;--复位信号m_w_in:inoutstd_logic;--写请求m_r_in:inoutstd_logic;--读请求c_w_out:outstd_logic;c_r_out:outstd_logic;k2:instd_logic;--节拍控制aluout_in:instd_logic_vector(7downto0);--Aluout输入dataFromMem:instd_logic_vector(7downto0);dataToMem

8、:outs