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1、代码一•顶层模块moduleMIPS_C(clk,rst,MIPS_out)；inputclk,rst;output[7:0]MIPS_out;wire[31:0]ALU_DC;wire[31:0]Pc_out;wire[5:0]op;wire[5:0]func;wireALUSrcA;wireALUSrcB;//wireLoad_Mem;wireMemtoReg;wireRegDst;wireExtOp;//wireMemWr;wireRegWr;wire[31:O]instruct;wirePcWrite;wire[31:0]imm32;wire[15
2、:0]imml6;wire[25:O]target;wire[31:0]rdata2;wire[31:O]rdatal;wire[31:O]rdata3;wireALU_CLK;wire[31:0]Mem_Dout;wire[4:0]rt;wire[4:0]rd;wire[4:0]rs;wire[31:0]ALU_DB;wire[31:0]ALU_DA;wire[31:0]wdata;wire[4:0]waddr;wireBranch;wireJump;wire[31:0]Mem_Din;wireALU_OverTlow;wireALU_ZERO;wire
3、[4:0]shamt;wire[4:0]ALU_SHIFT;assignMIPS_out=rdata3[7:0];Main_controlmain_control(.rst(rst),•op(op),.ALUSrcA(ALUSrcA),.ALUSrcB(ALUSrcB),.MemtoReg(MemtoReg),.RegDst(RegDst),.ExtOp(ExtOp),.PcWrite(PcWrite),.RegWr(RegWr),.clk(clk)Fetch_topfetch_top(.clk(clk)z.rst(rst),.instruct(instr
4、uct),.ALU_DA(ALU_DA),」ump(Jump),.Branch(Branch),.PcWrite(PcWrite),.ALU_DB(ALU_DB),.Pc_out(Pc_out));decodeDecode(.instruct(instruct),•op(op),•rs(rs),.rt(rt),.rd(rd),•func(func),.shamt(shamt),.target(target)regfileRegfile(.clk(clk),.rst(rst),.RegWr(RegWr),.waddr(waddr),・wdata(wdata)
5、,.raddrl(rs),.rdatal(rdatal),,raddr2(rt),・rdata2(rdata2),.rdata3(rdata3));/*Memorymem(.Mem_Adr(Mem_Adr),・MemWr(MemWr),.rst(rst),.clk(clk),・Mem_Din(rdata2),・Mem_Dout(Mem_Dout));*/.rst(rst),.ExtOp(ExtOp),.imm32(imm32));flagFlag(.ALU_DA(ALU_DA),.ALU_DB(ALU_DB),•op(op),•func(func),」um
6、p(Jump),.Branch(Branch));ALU_topalu_top(.ALU_CLK(clk),.rst(rst),•func(func),•op(op),.ALU_DA(ALU_DA),.ALU_DB(ALU_DB),.ALU_SHIFT(shamt),.ALU_ZERO(ALU_ZERO),.ALU_OverFlow(ALU_OverFlow),.ALU_DC(ALU_DC));data_selectDATA_select(.ALUSrcA(ALUSrcA),.ALUSrcB(ALUSrcB),・MemtoReg(MemtoReg)，.Re
7、gDst(RegDst),Jmm32(imm32),.target(target),.rdata2(rdata2),・rdatal(rdatal),.ALU_DC(ALU_DC),.Mem_Dout(Mem_Dout)/•rt(rt),.rd(rd),.ALU_DB(ALU_DB),.ALU_DA(ALU_DA),・wdata(wdata),・waddr(waddr));endmodule二.主控模块moduleMain^ontrolfcIk/s^op^LUSrcA^LUSrcB^emtoReg^egDstExtOp,PcWrite,RegWr)；inpu
8、tclkjst;input[5:0]op;outputregALU
