VHDL8分频输出分频器.doc

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1、libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitydivisport(clk:instd_logic;clear:instd_logic;clk_out:outstd_logic);enddiv;architectureaofdivissignaltem:integerrange0to7;beginp1:process(clear,clk)beginifclear='0'thentem<=0;elsifclk'eventandclk='1'the

2、niftem=7thentem<=0;elsetem<=tem+1;endif;iftem<4thenclk_out<='1';elseclk_out<='0';endif;endif;endprocessp1;enda;