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1、libraryieee;useieee.std_logic_1164.all;entitymulisport(a,b:instd_logic_vector(0to4);p:outstd_logic_vector(0to9));endmul;architectures_mulofmuliscomponentfaisport(a,b,ci:instd_logic;s,co:outstd_logic);endcomponent;signals1:std_logic_vector(1to12);signalc1:std_logic_vector(1to19);beginp(0)<=a(0)a
2、ndb(0);f11:faportmap((a(1)andb(0)),(a(0)andb(1)),'0',p(1),c1(1));f12:faportmap((a(2)andb(0)),(a(1)andb(1)),'0',s1(1),c1(2));f13:faportmap((a(3)andb(0)),(a(2)andb(1)),'0',s1(2),c1(3));f14:faportmap((a(4)andb(0)),(a(3)andb(1)),'0',s1(3),c1(4));f21:faportmap(s1(1),(a(0)andb(2)),c1(1),p(2),c1(5));f
3、22:faportmap(s1(2),(a(1)andb(2)),c1(2),s1(4),c1(6));f23:faportmap(s1(3),(a(2)andb(2)),c1(3),s1(5),c1(7));f24:faportmap((a(4)andb(1)),(a(3)andb(2)),c1(4),s1(6),c1(8));f31:faportmap(s1(4),(a(0)andb(3)),c1(5),p(3),c1(9));f32:faportmap(s1(5),(a(1)andb(3)),c1(6),s1(7),c1(10));f33:faportmap(s1(6),(a(
4、2)andb(3)),c1(7),s1(8),c1(11));f34:faportmap((a(4)andb(2)),(a(3)andb(3)),c1(8),s1(9),c1(12));f41:faportmap(s1(7),(a(0)andb(4)),c1(9),p(4),c1(13));f42:faportmap(s1(8),(a(1)andb(4)),c1(10),s1(10),c1(14));f43:faportmap(s1(9),(a(2)andb(4)),c1(11),s1(11),c1(15));f44:faportmap((a(4)andb(3)),(a(3)andb
5、(4)),c1(12),s1(12),c1(16));f51:faportmap(s1(10),c1(13),p(5),c1(17));f52:faportmap(s1(11),c1(17),c1(14),p(6),c1(18));f53:faportmap(s1(12),c1(18),c1(15),p(7),c1(19));f54:faportmap((a(4)andb(4)),c1(19),c1(16),p(8),p(9));ends_mul;
