实验八：利用有限状态机进行时序逻辑的设计.doc

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1、实验八：利用有限状态机进行时序逻辑的设计一：利用有限状态机进行时序逻辑的设计的源程序:moduleseqdet(x,z,clk,rst,state);inputx,clk,rst;outputz;output[2:0]state;reg[2:0]state;wirez;parameterIDLE='d0,A='d1,B='d2,C='d3,D='d4,E='d5,F='d6,G='d7;assignz=(state==E&&x==0)?1:0;always@(posedgeclk)if(!rst)beginstate<=I

2、DLE;endelsecasex(state)IDLE:if(x==1)beginstate<=A;endA:if(x==0)beginstate<=B;endB:if(x==0)beginstate<=C;endelsebeginstate<=F;endC:if(x==1)beginstate<=D;endelsebeginstate<=G;endD:if(x==0)beginstate<=E;endelsebeginstate<=A;endE:if(x==0)beginstate<=C;endelsebeginstat

3、e<=A;endF:if(x==1)beginstate<=A;endelsebeginstate<=B;endG:if(x==1)beginstate<=F;enddefault:state=IDLE;endcaseendmodule二：利用有限状态机进行时序逻辑的设计的测试代码：`timescale1ns/1ns`include"./seqdet.v"moduleseqdet_Top;regclk,rst;reg[23:0]data;wire[2:0]state;wirez,x;assignx=data[23];alw

4、ays#10clk=~clk;always@(posedgeclk)data={data[22:0],data[23]};initialbeginclk=0;rst=1;#2rst=0;#30rst=1;data='b1100_1001_0000_1001_0100;#500$stop;endseqdetm(x,z,clk,rst,state);endmodule三：Transcript显示结果：#ReadingE:/altera/91/modelsim_ase/tcl/vsim/pref.tcl#Loadingproje

5、ctfulladder8#readingE:altera91modelsim_asewin32aloem/../modelsim.ini#Loadingprojectssss#Compileofseqdet.vwassuccessful.#Compileofseqdet_Top.vwassuccessful.#2compiles,0failedwithnoerrors.vsimwork.seqdet_Top#vsimwork.seqdet_Top#Loadingwork.seqdet_Top#Loadingwork

6、.seqdet四：测试波形如下图所示：