计数器复习进程.doc

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1、计数器100进制计数器个位十位分开LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_unsigned.ALL;ENTITYcount100ISPORT(en,clk:INSTD_LOGIC;qa:outSTD_LOGIC_VECTOR(3DOWNTO0);--个位数计数qb:outSTD_LOGIC_VECTOR(2DOWNTO0);--十数计数rco:OUTSTD_LOGIC);--计数进位ENDcount100;ARCHITECTUREaOFcount

2、60ISBEGINprocess(clk)variabletma:STD_LOGIC_VECTOR(3DOWNTO0);variabletmb:STD_LOGIC_VECTOR(2DOWNTO0);beginif(clk'eventandclk='1')thenif(en='1')thenif(tma="1001")thentma:="0000";if(tmb=“1001”)thentmb:=“0000”;rco<=‘1’;elsetmb:=tmb+1;endif;elsetma:=tma+1;rco<=‘0’;end

3、if;endif;endif;qa<=tma;qb<=tmb;endprocess;ENDa;60进制不分十位个位libraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitylsyisport(clk:instd_logic;cq:outstd_logic_vector(7downto0);cout:outstd_logic);endlsy;architecturezhangoflsyisbeginprocess(clk)var

4、iablecqi:std_logic_vector(7downto0);beginifclk'eventandclk='1'thenifcqi<59thencqi:=cqi+1;elsecqi:=(others=>'0');endif;endif;ifcqi=59thencout<='1';elsecout<='0';endif;cq<=cqi;endprocess;endzhang;分频器50占空比1：1LIBRARYieee;USEieee.std_logic_1164.ALL;USEieee.std_logic_

5、unsigned.ALL;ENTITYcountISPORT(clk:inSTD_LOGIC;clkout:bufferSTD_LOGIC;ENDcount;ARCHITECTUREaOFcountISSignalcount:STD_LOGIC_vector(21downto0);BEGINPROCESS(clk)BEGINIF(clk'EVENTANDclk=‘1’)THENIF(count=“11001")THENcount=“00000”；clkout<=notclkout;ELSEcount=count+1；E

6、NDIF；ENDIF；ENDPROCESS；ENDa;使用vhdl语言设计程序，能够实现计算输入信号中1的个数。输入信号data为八位信号，输出y为三位信号，要求该程序能够计算出八位信号的八位中有几位信号是1libraryieee；useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entitydataisport(data:instd_logic_vector(7downto0);y:outstd_logic_vector(2downto0));endd

7、ata;architectureloopofdataisbeginp1:process(data)variabletmp:std_logic_vector(2downto0);begintmp:="000";foriin0to7loopifdata(i)='1'thentmp:=tmp+'1';endif;endloop;y<=tmp;endprocessp1;endloop;设计一个D触发器，输入信号为时钟clk，数据D[3:0]，复位端rst，输出为Q[3:0],要求分别设计同步复位D触发器和异步复位D触发器lib

8、raryieee;useieee.std_logic_1164.all;entitydffisport(clk,d,clr:instd_logic;q:outstd_logic);enddff;architecturedff2ofdffisbeginp1:process(clk,clr)beginif(clr='0')thenq<