单片机课件(黄英)：第2章_硬件结构 双语教学.ppt

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1、Chapter2:HardwarestructureofmicrocontrollerMicrocontrollerPrincipleandApplication主讲教师：黄英1Chapter2Hardwarestructureofmicrocontroller2.1Logicstructureandsignalpins2.2Internalmemory2.3ParallelInput/outputports2.4Clockcircuitandtiming2.5WorkingModes22.1.1Thefeaturesof8051core2

2、.1Logicstructureandsignalpins8051:ThecoreofMCS-51devicesTheoriginalmemberoftheMCS-51familiy8-bitCPUoptimizedforcontrolapplicationsExtensiveBooleanprocessing（single-bitlogic）capabilities64KProgramMemoryaddressspace64KDataMemoryaddressspace4KBytesofon-chipProgramMemory128By

3、tesofon-chipDataRAM32bidirectionalandindividuallyaddressableI/OlinesTwo16-bittimer/countersFullduplexUART5-sourceinterruptstructurewithtwoprioritylevelsOn-chipclockoscillator32.1LogicstructureandsignalpinsBlockDiagramof8051coreCPU4×8-bitI/OPortsTimer0SerialPortOSCInterrupt

4、ControlExternalinterruptsTimer12×16-bitTimer/Counter64KBBusExtendControlTxDRxDP0P1P2P3CounterInputs4K×8-bitROM128×8-bitRAM4TheInternalLogicStructureofAT89C5152.1Logicstructureandsignalpins2.1.2SignalPinsofAT89S5162.1Logicstructureandsignalpins72.2.1InternalDataMemory2.2In

5、ternalmemoryTheAT89C51has128bytesofon-chipRAMplusanumberofSFRs.SFR:SpecialFunctionRegisters82.2.1InternalDataMemoryFigure:Lower128bytesUpper128bytes92.2.1InternalDataMemoryRegisterArea:RegisterBanks（0、1、2、3）（32Bytes）BitAddressableArea（16Bytes）UserRAMArea（80Bytes）Thisare

6、acanbedividedinto3parts（1）Lower128bytesofInternalRAM102.2.1InternalDataMemoryFigureUserRAMarea:112.2.1InternalDataMemory（1）Lower128bytesofInternalRAMThisareaisgroupedinto4banksof8registers（R0～R7）Twobits,RS1andRS0,inProgramStatusWord（PSW）areforselectingwhichregisterbankis

7、inuse.（00、01、10、11）Thisallowsmoreefficacioususeofcodespace,sinceregisterinstructionsareshorterthaninstructionsthatusedirectaddressing.Theaddressesinthisareaare00Hthrough1FH.①RegistersArea:RegisterBanks（0、1、2、3）Resetdefaultistoregisterbank0.Resetinitial

8、izestheStackPointertolocation07H.Soinfactthestackbeginsfrom08H.But08H～1FHisregisterareath