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1、抢答鉴别电路myqdjb的vhdl源程序--myqdjb.vhdlibraryieee;useieee.std_logic_1164.all;entitymyqdjbisport(clr:instd_logic;a,b,c,d:instd_logic;a1,b1,c1,d1:outstd_logic;states:outstd_logic_vector(3downto0));endentitymyqdjb;architectureartofmyqdjbisconstantw1:std_logic_vector:="0001";c
2、onstantw2:std_logic_vector:="0010";constantw3:std_logic_vector:="0100";constantw4:std_logic_vector:="1000";beginprocess(clr,a,b,c,d)isbeginifclr='1'thenstates<="0000";elsif(a='1'andb='0'andc='0'andd='0')thena1<='1';b1<='0';c1<='0';d1<='0';states<=w1;elsif(a='0'andb='
3、1'andc='0'andd='0')thena1<='0';b1<='1';c1<='0';d1<='0';states<=w2;elsif(a='0'andb='0'andc='1'andd='0')thena1<='1';b1<='0';c1<='1';d1<='0';states<=w3;elsif(a='0'andb='0'andc='0'andd='1')thena1<='0';b1<='0';c1<='0';d1<='1';states<=w4;endif;endprocess;endarchitectureart
4、;计分器电路yjfq的vhdl源程序--yjfq.vhdlibraryieee;useieee.std_logic_1164.all;useieee.std_logic_unsigned.all;entityyjfqisport(rst:instd_logic;add:instd_logic;chos:instd_logic_vector(3downto0);aa2,aa1,aa0,bb2,bb1,bb0:outstd_logic_vector(3downto0);cc2,cc1,cc0,dd2,dd1,dd0:outstd_l
5、ogic_vector(3downto0));endentityyjfq;architectureartofyjfqisbeginprocess(rst,add,chos)isvariablepoints_a2,points_a1:std_logic_vector(3downto0);variablepoints_b2,points_b1:std_logic_vector(3downto0);variablepoints_c2,points_c1:std_logic_vector(3downto0);variablepoints
6、_d2,points_d1:std_logic_vector(3downto0);beginif(add'eventandadd='1')thenifrst='1'thenpoints_a2:="0001";points_a1:="0000";points_b2:="0001";points_b1:="0000";points_c2:="0001";points_c1:="0000";points_d2:="0001";points_d1:="0000";elsifchos="0001"thenifpoints_a1="1001
7、"thenpoints_a1:="0000";ifpoints_a2="1001"thenpoints_a2:="0000";elsepoints_a2:=points_a2+'1';endif;elsepoints_a1:=points_a1+'1';endif;elsifchos="0010"thenifpoints_b1="1001"thenpoints_b1:="0000";ifpoints_b2="1001"thenpoints_b2:="0000";elsepoints_b2:=points_b2+'1';endif
8、;elsepoints_b1:=points_b1+'1';endif;elsifchos="0100"thenifpoints_c1="1001"thenpoints_c1:="0000";ifpoints_c2="1001"thenpoints_c2:="0
