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1、VHDL语言的UART串行接口芯片设计程序清单附录1数据接收据器的VHDL语言描述清单LIBRARYIEEE;USEIEEE.STD_LOGIC_1164.ALL;useieee.std_logic_unsigned.all;useieee.std_logic_arith.all;useieee.std_logic_signed.all;ENTITYUART_receiverISPORT(RxD,Bclkx8,sysclk,reset,RDRF:INSTD_LOGIC; RDR:OUTS
2、TD_LOGIC_VECTOR(7DOWNTO0); setRDRF,setOE,setFE:OUTSTD_lOGIC);ENDUART_receiver;ARCHITECTURErtlOFUART_receiverISTYPEstateTYPEIS(R_WAiT,START_DETECTED,R_DATA);SIGNALstate,nextstate:stateTYPE;SIGNALRSR:STD_LOGIC_VECTOR(7DOWNTO0);SIGNALcnt1:INTEGERRAN
3、GE0TO7;SIGNALcnt2:INTEGERRANGE0TO8;signalclr1,clr2:std_logic;SIGNALinc1,inc2,shftRSR,loadRDR:STD_LOGIC;SIGNALBclkx8_Dlayed,Bclkx8_rising:STD_LOGIC;BEGINBclkX8_rising<=Bclkx8AND(NOTBclkx8_dlayed);R_control:PROCESS(state,RxD,RDRF,cnt1,cnt2,BclkX8_rising
4、)BEGIN--inc1<='0';inc2<='0';--clr1<='0';clr2<='0';shftRSR<='0';loadRDR<='0';setRDRF<='0';setOE<='0';setFE<='0';CASEstateIS WHENR_WAIT=> IF(Rxd='0')THENnextstate<=START_DETECTED; ELSEnextstate<=R_WAIT; ENDIF; WHENSTART_DETE
5、CTED=> IF(Bclkx8_rising='0')THEN nextstate<=START_DETECTED; ELSIF(RxD='1')THEN clr1<='1';nextstate<=R_WAIT; ELSIF(cnt1=3)THEN clr1<='1';nextstate<=R_WAIT; ELSE
6、 inc1<='1';nextstate<=START_DETECTED; ENDIF;WHENR_DATA=> IF(Bclkx8_rising='0')THENnextstate<=R_DATA;ELSEinc1<='1';IF(cnt1/=7)THENnextstate<=R_DATA;ELSIF(cnt2/=8)THEN shftRSR<='1';inc2<='1';clr1<='1'; nextstate<=R_DATA;ELSE Nextst
7、ate<=R_WAIT; setRDRF<='1';clr1<='1';clr2<='1'; IF(RDRF='1')THENsetOE<='1'; ELSIF(RXD='0')THENsetFE<='1'; ELSEloadRDR<='1'; ENDIF; ENDIF; ENDIF; ENDCASE;ENDPROCESS;R_update:PROCESS(sysclk,reset)BEGINIF(reset=
8、'0')THENstate<=R_WAIT;BclkX8_Dlayed<='0'; cnt1<=0;cnt2<=0;ELSIF(syscLk'EVENTANDsysclk='1')THEN state<=nextstate; IF(clr1='1')THENcnt1<=0; ELSIF(inc1='1')THENcnt1<=cnt1+1; ENDIF; IF(clr2='1')THENcnt2<=0; ELSIF(inc2='1')THENcnt2
