三人表决器 VHDL源程序.doc

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1、--三人表决器（三种不同的描述方式）vhdl--Three-inputMajorityVoter--Theentitydeclarationisfollowedbythreealternativearchitectureswhichachievethesamefunctionalityindifferentways.ENTITYmajISPORT(a,b,c:INBIT;m:OUTBIT);ENDmaj;--DataflowstylearchitectureARCHITECTUREconcurre

2、ntOFmajISBEGIN--selectedsignalassignmentstatement(concurrent)WITHa&b&cSELECTm<='1'WHEN"110"

3、"101"

4、"011"

5、"111",'0'WHENOTHERS;ENDconcurrent;--StructuralstylearchitectureARCHITECTUREstructureOFmajIS--declarecomponentsusedinarchitectureCOMPONENTand2PORT(i

6、n1,in2:INBIT;out1:OUTBIT);ENDCOMPONENT;COMPONENTor3PORT(in1,in2,in3:INBIT;out1:OUTBIT);ENDCOMPONENT;--declarelocalsignalsSIGNALw1,w2,w3:BIT;BEGIN--componentinstantiationstatements.--portsofcomponentaremappedtosignals--withinarchitecturebyposition.gate

7、1:and2PORTMAP(a,b,w1);gate2:and2PORTMAP(b,c,w2);gate3:and2PORTMAP(a,c,w3);gate4:or3PORTMAP(w1,w2,w3,m);ENDstructure;--Behaviouralstylearchitectureusingalook-uptableARCHITECTUREusing_tableOFmajISBEGINPROCESS(a,b,c)CONSTANTlookuptable:BIT_VECTOR(0TO7):=

8、"00010111";VARIABLEindex:NATURAL;BEGINindex:=0;--indexmustbeclearedeachtimeprocessexecutesIFa='1'THENindex:=index+1;ENDIF;IFb='1'THENindex:=index+2;ENDIF;IFc='1'THENindex:=index+4;ENDIF;m<=lookuptable(index);ENDPROCESS;ENDusing_table;