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1、libraryieee;useieee.std_logic_1164.all;useieee.std_logic_arith.all;useieee.std_logic_unsigned.all;useieee.std_logic_signed.all;entitymy_trafficisPORT(clk,en:INSTD_LOGIC;lampa,lampb:outSTD_LOGIC_VECTOR(3DOWNTO0);--lampa-LRYG,lampb-LRYGled_disp1,led_disp2,led_disp
2、3,led_disp4:outSTD_LOGIC_VECTOR(6DOWNTO0));ENDmy_traffic;ARCHITECTUREmy_traffic_aOFmy_trafficISsignalastate,bstate,astate_temp,bstate_temp:std_logic_vector(2downto0);--状态编码信号signalnum_a,num_b:unsigned(7downto0);--计时integerrange0to65;signalctla,ctlb,clk1:std_logi
3、c;--A、B两个方向上的控制位和分频后的秒信号componentdecled--定义译码显示元件port(datain:inunsigned(3downto0);dataout:outstd_logic_vector(6downto0));endcomponent;componentfenpin--定义分频器（分频，50Hz的时钟变成1HZ的秒信号）PORT(clkin:INSTD_LOGIC;clkout:OUTSTD_LOGIC);endcomponent;BEGINprocess(clk1,astate_tem
4、p,bstate_temp)--状态寄存器进程beginifrising_edge(clk1)thenastate<=astate_temp;bstate<=bstate_temp;endif;endprocess;a_ctl:process(clk1,num_a,astate)--A方向的情况beginifrising_edge(clk1)thenifen='1'thenifctla='1'thenctla<='0';caseastateiswhen"000"=>lampa<="0001";--AGnum_a<=x"
5、40";--对其赋初值40sastate_temp<="001";when"001"=>lampa<="0010";--AYnum_a<=x"05";--对其赋初值5sastate_temp<="010";when"010"=>lampa<="1000";--ALnum_a<=x"15";--对其赋初值15sastate_temp<="011";when"011"=>lampa<="0010";--AYnum_a<=x"05";--对其赋初5sastate_temp<="100";when"100"=>lampa<="
6、0100";--ARnum_a<=X"55";--对其赋初55sastate_temp<="000";whenothers=>null;endcase;elsifctla='0'thenifnum_a=1thenctla<='1';elseifnum_a(3downto0)=0thennum_a(3downto0)<="1001";--当低位为0时，变为9num_a(7downto4)<=num_a(7downto4)-1;--高位减1elsenum_a(3downto0)<=num_a(3downto0)-1;--低
7、位减1endif;endif;endif;elsectla<='1';astate_temp<="000";endif;endif;endprocessa_ctl;b_ctl:process(clk1,num_b,bstate)--B方向的情况beginifrising_edge(clk1)thenifen='1'thenifctlb='1'thenctlb<='0';casebstateiswhen"000"=>lampb<="0100";--BRnum_b<=X"65";--对其赋初值65sbstate_temp<
8、="001";when"001"=>lampb<="0001";--BGnum_b<=X"30";--对其赋初值30sbstate_temp<="010";when"010"=>lampb<="0010";--BYnum_b<=X"05";--对其赋初值5sbstate_temp<="011";when"011"=>lampb<=
