SynthesisOptimization-综合优化,来自synopsys.pdf

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1、SynthesisOptimizationTimingOptimizationsSettingsUserealisticdesignconstraints,about10-15%oftherealgoal.Overconstrainingyourdesigncanbecounter-productive.Useclock,falsepath,andmulticyclepathconstraintstomaketheconstraintsrealistic.Selectabalancedfanoutconstraint.Alargeconstrai

2、ntcreatesnetswithlargefanouts,andalowfanoutconstraintresultsinreplicatedlogic.Ifthecriticalpathgoesthrougharithmeticcomponents,trydisablingResourceSharing.YoucangetfasterTimesattheexpenseofincreasedarea,butusethistechniquecarefully.IftheP&Randsynthesistoolsreportdifferentcrit

3、icalpaths,useatimingconstraintwiththe-routeoption.ForFSMs,usetheonehotencodingstyle,becauseitisoftenthefastestimplementation.IfalargeoutputdecoderfollowsanFSM,grayorsequentialencodingcouldbefaster.Fordesignswithblackboxes,characterizethetimingmodelsaccurately,usingthesyn_tpd,

4、syn_tco,andsyn_tsodirectives.Makesurethatyoupassyourtimingconstraintstotheplace-and-routetools,sothattheycanusetheconstraintstooptimizetiming.2Re-timingFSMCompiler&FSMExplorerShannonExpansionOperandReorderingSettingFanoutLimitsRouteConstraint3Re-timingWhatisRe-timing>

5、AutomaticallymovingregistersacrosscombinatoriallogictoimprovetimingwhileensuringidenticallogicbehaviorUpto20%Faster(ave.5%)Retimingistimingbased4RetimingRetimingintheSynplifyProtoolisregisterbalancingRegistersmovedacrosscombinatoriallogictoimprovetimingTimingdrivenGlobal

6、SettingGlobalswitchinProjectwindowAssignmentbysyn_allow_retimingattributeGlobalGlobalSettingIndividualregisterLocalSetting5RetimingExampleBeforeRetiming[2]clk[1][2:0][0][0][1][0]outputnput1[2:0]DQ[0]ff_0_.Q[2]output.G_3g1g1_1.G_2nput2[2:0][2:0]NamesoftheregistersThisattri

7、butemarkstheregisterasonecreatedasaresultof[1]DQ[1]thatcanbemovedduringretiming,butretiming,andwhichdidnotexistintheRTLff_1_.Qdoesnotnecessarilyforceittobemovedview.Theaddedduringretimingregistershavea_retsuffix[2]DQ[2]AfterRetimingff_2_.Qclk[2][1][1][0]output[0]DQ[2:0][2]npu

8、t1[2:0]output.G_3ff_ret.Qg1g1_1.G_2[2:0]nput2[2:0]6Herearesomeimpli