AHDL语法入门（Altera公司提供）

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1、AHDLTrainingClassDannyMokAlteraHKFAE(dmok@altera.com)9/19/2021P.1WhatisAHDLAlteraHardwareDescriptionLanguagedevelopbyAlteraintegrateintotheAlterasoftwareMax+PlusIIdescriptionthehardwareinlanguageinsteadofgraphiceasytomodifyeasytomaintaneverygoodforcomplexcombinationallogicB

2、CDto7Segmentconverteraddressdecodingstatemachinemorethanyouwant……..9/19/2021P.2continue...AseasyasGraphicEntryAspowerfulasHDL(HardwareDescriptionLanguage)VHDL,VerilogHDLetc.9/19/2021P.3HowtousetheADHLuseanytexteditortocreatethefileAlteraSoftwareMax+PlusIIprovidetexteditorCli

3、ckthebuttonTypeinyourAHDLdesignfile9/19/2021P.4continue…..CreateyourAHDLfile9/19/2021P.5continue…..saveyourADHLfileasname.TDFMustbethesame9/19/2021P.6continue...Clickonthisicon9/19/2021P.7ErrorLocationduringCompilationEasytolocatetheerrorClicktheerrormessageClicktheLocatebut

4、tonErrorlocation9/19/2021P.8AHDLTemplateIforgot…….If-then-elsecase-endcaseloop-endloop??…???Modifythecode9/19/2021P.9GeneralAHDLFormatSUBDESIGNdecode1(input_pin_name:INPUT;input_bus_name[15..0]:INPUT;output_pin_name:OUTPUT;output_bus_name:OUTPUT;)BEGINouptut_pin_name=input_p

5、in_name;output_bus_name=input_bus_name;END;KeyWordDefienI/OportLogicAHDLformat9/19/2021P.10YourFirstAHDLdesign--AddressDecoderChip_enable=a0&a1&a2&!a3SUBDESIGNdecode1(a[3..0]:input;chip_enable:output;)beginchip_enable=(a[3..0]==H"7");end;9/19/2021P.11WhyIuseAHDLinsteadofGrap

6、hicEasytoModifyDocumentduringthecodingIwanttodecodeH”A”notH”7”SUBDESIGNdecode1(a[3..0]:input;chip_enable:output;)beginchip_enable=(a[3..0]==H"A");end;SelfExplaintheFunctionOnlythingtochangeNeedmoreefforttomodifyChip_enable=!a0&a1&!a2&a39/19/2021P.12MoreSUBDESIGNdecode1(a[3..

7、0]:input;chip_enable:output;)beginchip_enable=(a[3..0]==B"1x0x");end;Somebitcanbeignoreforcomparsion9/19/2021P.13SomethingyouneedtoknowAddition:+Subtraction:-NumericEquality:==Notequalto:!=Greaterthan:>Greaterthanorequalto:>=Lessthan:

8、D:&9/19/2021P.14UseConstantFunctionUseConstantifthesamenumber,textstring,or