EDA试验-数字时钟实验报告

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1、EDA试验——数字时钟一.实验目的(1)熟悉在EDA平台上进行数字电路集成设计的整个流程。(2)掌握MaxPlus软件下的简单的图形、VHDL文本等输入的设计方法。(3)学习使用JTAG借口下载逻辑电路到可编程芯片，并能调试到芯片正常工作。二.实验原理本实验是实现数字电子钟，直接用数字显示时间的计时装置。分别设计出时间设置电路，走时电路，打铃控制电路，显示电路。三.实验设计(1)在这个设计中我使用VHDL设计时间设置电路：LIBRARYIEEE;USEIEEE・STD_L0GTC_1164・ALL;USEIEEE.STD_LOGIC_UNSIGNED.ALL;US

2、EIEEE•STD_LOGIC_ARITH.ALL;ENTITYcontrolISPORT(reset:INSTD_LOGIC;begend:INSTD_LOGIC;keyup:INSTD_LOGIC;enter:INSTD_LOGIC;settime:OUTSTD_LOGIC;hourhset:OUTINTEGERRANGE0TO2;hourlset:OUTINTEGERRANGE0TO9;minhset:OUTINTEGERRANGE0TO5；minlset:OUTINTEGERRANGE0TO9；sechset:OUTINTEGERRANGE0TO5；sec

3、lset:OUTINTEGERRANGE0TO9)；ENDcontrol;ARCHITECTUREarchiOFcontrolISTYPESTATEIS(sethh,sethlzsetmh,setml,setshAsetsl,ini);SIGNALadjsta:STATE;SIGNALsetmark:STD_LOGIC;SIGNALseclow,minlow,hourlow:INTEGERRANGE0TO9;SIGNALsechighAminhigh:INTEGERRANGE0TO5;SIGNALhourhigh:INTEGERRANGE0TO2;BEGINsee

4、lset<=seclow;sechset<=sechigh;minlset<=min1ow;minhset<=minhigh;hourlset<=hourlow;hourhset<=hourhigh;settime<=setmark;mark:PROCESS(begend)beginifreset=111thensetmark<=101;elsifbegend1eventandbegend=111thenifsetmark=111thensetmark<=!01;elsesetmark<=111;endif;endif;ENDPROCESS;normal_run:

5、PROCESS(enter,reset)BEGINIFreseTHENadjsta<=ini;ELSIFenter=f11ANDenter1eventTHENcaseadjsteISWHENini=>adjsta<=sethh;WHENsethh=>adjsta<=sethl;WHENsethl=>adjsta<=setmh;WHENsetmh=>adjs丄；WHENsetml=>adjsta<=setsh;WHENsetsh=>adjsta<=setsl;WHENsetsl=>adjsta<=sethh;endcase;ENDIF;ENDPROCESS；time

6、_adjust:PROCESS(keyup)BEGINifreset=!11thenhourhigh<=0;hourlow<=0;minhigh<=0;minlow<=0;sechigh<=0;seclow<=0;elsifkeyup=*11ANDkeyup1eventTHENcaseadjstaISWHENsethh=>hourhigh<=hourhigh+l;WHENsethl=>hourlow<=hourlow+l;WHENsetmh=>minhigh<=minhigh+l;WHENsetml=>minlow<=minlow+l;WHENsetsh=>sec

7、high<=sechigh+l;WHENsetsl=>seclow<=seclow+l;WHENini=〉NULL;endcase;endif;ENDPROCESS；ENDarchi;走时电路：libraryieee;useieee•std_logic_ll64•all;useieee•std_logic_unsignedeall;useieee•std_logic_arith.all;entityclockisport(elk:instd_logic;settime:instd_logic;hourhset:inintegerrange0to2;hourlset

8、:inin