EDA实验：可变模计数器

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1、EDA实验：可变模计数器文档包括错误程序分析和正确程序及其注释。通过拨码开关SW1,SWO实现计数器模值的选择，可选的模值有12进制、24进制、30进制、60进制。First.vhdl原版本程序以及错误分析LIBRARYIEEE;USEIEEE.STDLOGIC1164.ALL;USEIEEE.STDLOGICUNSIGNED.ALL;WMM•ENTITYhoumingzhen051ISPORT(CLKJNSTD_LOGIC;Ml,M0:INSTD_LOGIC;A:OUTINTEGERRANGE0TO60;-在这里混淆了数据対象和变量的定义

2、B,C:OUTINTEGERRANGE0TO9;-A原意指计数数据，B,C分别表示计数数值的十位和个位，本应是过程变量DATA_OUT1,DATA_OUT2:OUTSTD_LOGIC_VECTOR(6DOWNTO0)一定义两个标准逻辑矢量，分别作为两位数码管的输入)；ENDhoumingzhen051;ARCHITECTUREbehOFhoumingzhen051ISBEGINPROCESS(CLK)-这里应该有分频，使得计数时长为1SIFCLK'EVENTANDCLK=1THENELSIF(MO=OANDMl=0)THENIF(A>11)

3、THENA:=0;ELSIF(A=11)THENA:=0;ELSEA:=A+1;ENDIFELSIF(M0=0ANDMl=l)THENIF(A>23)THENA:=0;ELSE(A=23)THENA:=0;ELSEA:=A+1;ENDIF;ELSIF(MO=1ANDM1=O)THENIF(A>29)THENA:=0;ELSIF(A=29)THENA:=0ELSEA:=A+1;ENDIF;ELSIF(MO=1ANDMl=l)THENIF(A>59)THENA:=0;ELSIF(A=59)THENA:=0;ELSEA:A+1;ENDIF;END

4、IF;B:AREM10;C:=A/10;“由于编译一肓出问题，反复修改最示也把这caseBiswhen0DATA_OUT<="0000001n;里改出了问题when1DATAOUTvJlOOlllU;when2DATA_OUT<=U0010010";when3DATA_OUT<="OOOOHO";when4DATA_OUT<="1001100H;when5DATA_OUT<="0100100H;when6DATA_OUT<=n0100000n;when7DATA_OUT<="OOOH11";when8DATA_OUT<="0000000";

5、when9DATA_OUT<="0000100H;endcase;caseCiswhen0DATA_OUT<="0000001";when1DATA_OUTv二”1001111”；when2DATA_OUT<=H0010010n;when3DATA_OUT<=,,OOOOHO,';when4DATAOUT<="1001100H;when5DATA_OUT<=n0100100H;when6DATA_OUT<=,,0100000H;when7DATA_OUT<=nOOOHll";when8DATA_OUT<=nOOOOOOO";when9DAT

6、A_OUT<=n0000100n;endcase;ENDPROCESS(CLK);ENDbeh;缺少时钟分频函数-总的来说，问题主耍是变量定义错误、Newversion

7、部接口情况PORT(CLK:INSTD_LOGIC;引脚：PIN_N2MO:INSTD_LOGIC;SWO和SW1的输入引脚：PIN_N25PIN_N26Ml:INSTD_LOGIC;管显示输入ENDENTITYhoumingzhen051;ARCHITECTUREBEHAVOFhoumingzhen051ISSIGNALCLK1HZ:STDLOGIC;BEGINTEMPI:PROCESS(CLK)VARIABLECNT1:INTEGER:=O;VARIABLECNT2:INTEGER:=24999999;BEGIN50MHz的时钟下需要0

8、.5sIFCLK'EVENTANDCLK=1THEN好等于一个时钟周期=lsIF(CNT1=CNT2)THENCNT1:=O;CLK1HZ<=NOTCLK1HZ;ELSECNT1