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1、ReconfigurableReadback-SignalGeneratorBasedonaField-ProgrammableGateArrayJinghuanChen,JaekyunMoon,andKiaBazargan,Member,IEEEAbstract—Wehavedesignedareadback-signalgeneratortoprovidenoise-corruptedsignalstoareadchannelsimulator.ItisimplementedinaXilinxVirtex-Efield-programmablegatearray(FPGA
2、)device.Thegeneratorsimulatesinhardwarethenoiseprocessesanddistortionsobservedinharddrives.Itusesembeddednonuniformrandomnumbergeneratorstosimulatetherandomcharacteristicsofvariousdisturbancesintheread/writeprocess.Thesignalgeneratorcansimulatereadbackpulses,intersymbolinterference,transiti
3、onnoise,electronicsnoise,headandmedianonlinearity,intertrackinterference,andwritetimingerroraccordingtothecharacteristicsspecifiedbytheuser.Asampleimplementationoperatesata70-MHzclockspeed.Thedesigncaneasilybescaledfordifferenterrorrates.Thegeneratorcanbereconfiguredinrealtimetogivetheuserf
4、lexibilityandincreasethecapacityoftheFPGAdevice.Thereadback-signalgeneratorcanbeintegratedintoanFPGAreadchannelsimulatororserveasatestbenchfordata-recoverycircuits.IndexTerms—Fieldprogrammablegatearray(FPGA),Gaussianpseudorandomnumbergenerator,magneticrecording,readchannel,readchannelmodeli
5、ng,reconfigurablecomputing,transitionnoise.I.INTRODUCTIONINTENSIVEsimulationisoftencarriedouttoinvestigateadvancedsignalprocessingtechniquesfordatastorageapplications.Thesimulationisnormallyperformedinsoftwarethatmaytakeaverylongtime.Forinstance,thesimulationofa10bit-errorrate(BER),assuming
6、10biterrorsareobserved,cantakedaysrunningonapersonalcomputerequippedwitha1-GHzPentiumIVprocessor.Ontheotherhand,thetargetsectorretryrates[i.e.,unrecoverableerrorratesaftererror-correction-code(ECC)]incommercialharddrivesnormallygobelow10fordesktopproductsand10forserver-classproducts.Oneappr
7、oachtospeedupthesimulationprocessistoimplementthewholesimulatororpartofitinhardware.Becausethenoisecharacteristicsinharddrivesareunique,theadditivewhiteGaussiannoise(AWGN)assumption,whichiswidelyacceptedinstudyingtheperformanceofmanycommunicationsystems,
