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1、234V.KLEDROWETZ,J.HAZE,BASICBLOCKOFPIPELINEDADCDESIGNREQUIREMENTSBasicBlockofPipelinedADCDesignRequirementsVilemKLEDROWETZ,JiriHAZEDept.ofMicroelectronics,BrnoUniversityofTechnology,Technicka3058/10,61600Brno,CzechRepublickledrowetz@phd.feec.vutbr.cz,haze@feec.vutbr.czAbstract.Th
2、epaperdescribesdesignrequirementsofpassesintothesub-DACwhichconvertsitbacktotheabasicstage(calledMDAC-MultiplyingDigital-to-analogsignal.ThisanalogsignalissubtractedfromtheAnalogConverter)ofapipelinedADC.Thereexisterrororiginalsampledsignalvin.Theresidualsignalgoesintosourcessuch
3、asfiniteDCgainofopamp,capacitortheopampwhereitisamplifiedtothefullscalerange.Themismatch,thermalnoise,etc.,arisingwhentheswitchedresiduefor1.5-bitstageisexpressedmathematicallybycapacitor(SC)techniqueandCMOStechnologyareused.ଵThesenon-idealitiesareexplainedandtheirinfluencesonݒif
4、ܸെݒ2ൌ௦ݒସܸ,(1)overallparametersofapipelinedADCarestudied.TheଵpipelinedADCincludingnon-idealitieswasmodeledinݒifܸݒ2ൌ௦ݒ൏െସܸ,(2)MATLAB-Simulinksimulationenvironment.ݒ2ൌ௦ݒotherwise(3)wherevinisinputsignalofMDACandVrefisvoltageKeywordsreference,whichdepend
5、sonthemaximuminputsignalswing.PipelinedADC,MDAC,SCtechnique,MATLABmodel,thermalnoise,opamp.2.MDACDesignRequirements1.IntroductionMDACconsistsoffourparts-sampleandholdstage,sub-ADC,sub-DACandsubtractingandamplifyingstage.ApipelinedADCarchitectureoffersgoodtrade-offAllthesepartsare
6、sourcesofnon-idealities.Itisnecessarybetweenconversionrate,resolutionandpowercon-toknowimportantblocks,whichhaveindispensablesumption.Fig.1showsaconventionalpipelinedADCinfluenceontooverallproperties,toachievegoodarchitecture.Itconsistsofseveralcascadedstages(eachparameterssuchas
7、resolution,powerconsumptionandresolven–bit),timingcircuitsanddigitalcorrectionblock.speed.Theconcurrentoperationofallpipelinedstagesmakesthisarchitecturesuitabletoachieveveryhighconversionrates.Theoverallspeedisdeterminedbythespeedofthesingle2.1MDACResolutionstage.Itisadifficulto
8、ptimizationproblemtodeterminetheoptimaln
