An efficient FPGA-based dynamic partial reconfiguration design flow and environment for image and signal processing IP cores

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1、ARTICLEINPRESSSignalProcessing:ImageCommunication25(2010)377–387ContentslistsavailableatScienceDirectSignalProcessing:ImageCommunicationjournalhomepage:www.elsevier.com/locate/imageAnefficientFPGA-baseddynamicpartialreconfigurationdesignflowandenvironmentforimageandsignalproces

2、singIPcoresa,b,b,cadB.Krill,A.Ahmad,A.Amira,H.RabahaNanotechnologyandIntegratedBio-EngineeringCentre(NIBEC),FacultyofComputingandEngineering,UniversityofUlster,JordanstownCampus,NewtownabbeyCo.Antrim,BT370QBBelfast,NorthernIrelandbDepartmentofElectronicandComputerEngineerin

3、g,SchoolofEngineeringandDesign,BrunelUniversity,WestLondon,UB83PHUxbridge,UKcDepartmentofComputerEngineering,FacultyofElectricalandElectronicEngineering,UniversitiTunHusseinOnnMalaysia(UTHM),86400BatuPahat,Johor,MalaysiadLaboratoired’Instrumentation,ElectroniquedeNancy,Unive

4、rsityHenriPoincare,540003Nancy,FrancearticleinfoabstractArticlehistory:Thispaperdescribesadynamicpartialreconfiguration(DPR)designflowandReceived30October2009environmentforimageandsignalprocessingalgorithmsusedinadaptiveapplications.Accepted26April2010Basedontheevaluationofthe

5、existingDPRdesignflow,importantfeaturessuchasoverallflexibility,applicationandstandardisedinterfaces,hostapplicationsandDPRKeywords:area/sizeplacementhavebeentakenintoconsiderationintheproposeddesignflowandDynamicpartialreconfiguration(DPR)environment.Threeintellectualproperty(I

6、P)coresusedinpre-processingandDesignflowtransformblocksofcompressionsystemsincludingcolourspaceconversion(CSC),Fieldprogrammablegatearray(FPGA)two-dimensionalbiorthogonaldiscretewavelettransform(2-DDBWT)andIPcoresthree-dimensionalHaarwavelettransform(3-DHWT)havebeenselectedto

7、validateImageandsignalprocessingtheproposedDPRdesignflowandenvironment.Resultsobtainedrevealthattheproposedenvironmenthasabettersolutionproviding:ascriptableprogramtoestablishthecommunicationbetweenthefieldprogrammablegatearray(FPGA)withIPcoresandtheirhostapplication,powercons

8、umptionestimationforpartialreconfigurationareaandautomaticgenerationofthepar