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1、REUSEMETHODOLOGYMANUALTrademarkInformationSynopsys,COSSAP,andLogicModelingareregisteredtrademarksofSynopsys,Inc.Cyclone,Formality,FloorplanManager,ModuleCompiler,PowerCompiler,SWIFTInterface,TestCompiler,VSSExpert,andVSSProfessionalaretrademarksofSyn-opsys,Inc.MentorGraphicsisaregisteredtradema
2、rkofMentorGraphicsCorporation.DFTAdvisor,FastScan,FISPbus,FlexTest,QuickPower,QuickSimII,andSeamlessCVEaretrademarksofMentorGraphicsCorporation.Allothertrademarksaretheexclusivepropertyoftheirrespectiveholdersandshouldbetreatedassuch.REUSEMETHODOLOGYMANUALFORSYSTEM-ON-A-CHIPDESIGNSbyMichaelKeat
3、ingSynopsys,Inc.PierreBricaudMentorGraphicsCorporationTableofContentsForeword....................................................................................xiiiAcknowledgements.....................................................................xv1Introduction..............................
4、......................................................11.1GoalsofThisDocument................................................................................21.1.1Assumptions.....................................................................................31.1.2Definitions....................
5、....................................................................31.1.3VirtualSocketInterfaceAlliance.....................................................41.2DesignforReuse:TheChallenge..................................................................41.2.1DesignforUse.......................
6、...........................................................51.2.2DesignforReuse..............................................................................51.2.3FundamentalProblems.....................................................................62TheSystem-on-a-ChipDesignProcess..........
7、...............................72.1ACanonicalSoCDesign...............................................................................72.2SystemDesignFlow.............................................................................
