VHDL复杂电路描述方法

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1、第六讲复杂电路的描述方法ECE545IntroductiontoVHDLVHDLforSpecificationVHDLforSimulationVHDLforSynthesisECE545IntroductiontoVHDLLevelsofdesigndescriptionAlgorithmiclevelRegisterTransferLevelLogic(gate)levelCircuit(transistor)levelPhysical(layout)levelLevelofdescriptio

2、nmostsuitableforsynthesisECE545IntroductiontoVHDLRegisterTransferLogic(RTL)DesignDescriptionCombinationalLogicCombinationalLogicRegisters…Today’sTopicECE545IntroductiontoVHDLVHDLDesignStylesComponentsandinterconnectsstructuralVHDLDesignStylesdataflowCo

3、ncurrentstatementsbehavioralRegistersStatemachinesTestbenchesSequentialstatementsSubsetmostsuitableforsynthesisVHDL的执行语句描述结构体中电路硬件的变化特点；结构体中的任何执行语句都是并行语句；并行语句的种类有：赋值类语句：数据流描述(逻辑函数的运算)元件类语句：结构描述（逻辑符号的连接）进程语句：行为描述（电路功能的流程）ECE545IntroductiontoVHDLXOR3Examp

4、leECE545IntroductiontoVHDLEntity(XOR3Gate)entityXOR3isport(A:inSTD_LOGIC;B:inSTD_LOGIC;C:inSTD_LOGIC;RESULT:outSTD_LOGIC);endXOR3;ECE545IntroductiontoVHDLDataflowArchitecture(XOR3Gate)architectureXOR3_DATAFLOWofXOR3issignalU1_OUT:STD_LOGIC;beginU1_OUT<=

5、AxorB;RESULT<=U1_OUTxorC;endXOR3_DATAFLOW;U1_outXOR3ECE545IntroductiontoVHDLStructuralArchitecture(XOR3Gate)architectureXOR3_STRUCTURALofXOR3issignalU1_OUT:STD_LOGIC;componentXOR2isport(I1:inSTD_LOGIC;I2:inSTD_LOGIC;Y:outSTD_LOGIC);endcomponent;beginU1:

6、XOR2portmap(I1=>A,I2=>B,Y=>U1_OUT);U2:XOR2portmap(I1=>U1_OUT,I2=>C,Y=>RESULT);endXOR3_STRUCTURAL;ABCRESULTXOR3ECE545IntroductiontoVHDLBehavioralArchitecture(XORGate)architectureXOR3_BEHAVIORALofXOR3isbeginXOR3_BEHAVE:process(A,B,C)beginif((AxorBxorC)='1

7、')thenRESULT<='1';elseRESULT<='0';endif;endprocessXOR3_BEHAVE;endXOR3_BEHAVIORAL;ECE545IntroductiontoVHDLDataflowDescriptionDescribeshowdatamovesthroughthesystemandthevariousprocessingsteps.DataFlowusesseriesofconcurrentstatementstorealizelogic.Concurre

8、ntstatementsareevaluatedatthesametime;thus,orderofthesestatementsdoesn’tmatter.DataFlowismostusefulstylewhenseriesofBooleanequationscanrepresentalogic.ECE545–IntroductiontoVHDLData-flowVHDLconcurrentsignalassignment()conditional