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1、IEEEJOURNALONSELECTEDAREASINCOMMUNICATIONS,VOL.27,NO.6,AUGUST2009985High-ThroughputLayeredDecoderImplementationforQuasi-CyclicLDPCCodesKaiZhang,StudentMember,XinmingHuang,Member,IEEE,ZhongfengWang,SeniorMember,IEEEAbstract—Thispaperpresentsahigh-throughputdecoderLDPCcodescanbeeffectivelydec
2、odedusingthestandarddesignfortheQuasi-Cyclic(QC)Low-DensityParity-Checkbelief-propagation(BP)algorithm,alsocalledsum-productal-(LDPC)codes.Twonewtechniquesareproposed,includinggorithm(SPA).Twophasesofmessages,thecheck-to-variableparallellayereddecodingarchitecture(PLDA)andcriticalpath(CTV)m
3、essagesandthevariable-to-check(VTC)messages,splitting.PLDAenablesparallelprocessingforalllayersbyestablishingdedicatedmessagepassingpathsamongthem.ThearetransmittedalongtheedgesoftheTannergraphtoupdatedecoderavoidscrossbar-basedlargeinterconnectnetwork.Crit-eachotheriteratively.Tosimplifyth
4、eBPalgorithm,min-sumicalpathsplittingtechniqueisbasedonarticulateadjustmentofalgorithm[7]–[9]isintroducedtoreducethecomplexityofthestartingpointofeachlayertomaximizethetimeintervalsthechecknodeoperations.Also,in[10],[11],onlyvariablebetweenadjacentlayers,suchthatthecriticalpathdelaycan(colu
5、mn)summationsarestoredduringtheBPalgorithmtobesplitintopipelinestages.Furthermore,min-sumandlooselycoupledalgorithmsareemployedforareaefficiency.Asacasereducememorysize,whichiscalledthelooselycoupledstudy,arate-1/22304-bitirregularLDPCdecoderisimplementedalgorithmin[12].Inparticular,theafore
6、mentionedtechniquesusingASICdesignin90nmCMOSprocess.Thedecodercancanbeemployedtoreducethehardwarecomplexityinmes-achievethemaximumdecodingthroughputof2.2Gbpsat10sageupdateunitsandtoreducethestoragememoriesfortheiterations.Theoperatingfrequencyis950MHzaftersynthesis2propagationmessages.andth
7、echipareais2.9mm.Generally,theexistingworkinLDPCdecoderarchitecturesIndexTerms—Low-densityparity-checkcodes,quasi-cycliccanbeclassifiedintothreecategories:fullyparallelmethodcodes,parallelarchitecture,layereddecoding,criticalpathsplit-[13],serialmethod[14