Computer Architecture and Parallel Computing

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1、ComputerArchitectureandParallelComputing并行结构与计算Lecture2-PipeliningPengLiuDept.ofInfo.Sci.&Elec.Engg.ZhejiangUniversityliupeng@zju.edu.cnMay18,2015•MicrocodingbecamelessattractiveasgapbetweenRAMandROMspeedsreduced•Complexinstructionsetsdifficulttopipeline,sodifficulttoincreaseperformanceasgatecou

2、ntgrew•IronLawexplainsarchitecturedesignspace–Tradeinstructions/program,cycles/instruction,andtime/cycle•Load-StoreRISCISAsdesignedforefficientpipelinedimplementations–Verysimilartoverticalmicrocode–InspiredbyearlierCraymachines(moreontheselater)2AnIdealPipelinestagestagestagestage1234•Allobject

3、sgothroughthesamestages•Nosharingofresourcesbetweenanytwostages•Propagationdelaythroughallpipelinestagesisequal•TheschedulingofanobjectenteringthepipelineisnotaffectedbytheobjectsinotherstagesTheseconditionsgenerallyholdforindustrialassemblylines,butinstructionsdependoneachother!3PipelinedMIPSTo

4、pipelineMIPS:•FirstbuildMIPSwithoutpipeliningwithCPI=1•Next,addpipelineregisterstoreducecycletimewhilemaintainingCPI=14UnpipelinedDatapathforMIPSPCSrcRegWriteMemWriteWBSrcbrrindjabspc+40x4AddAddclkweclkrs1rs2PCaddr31rd1weinstwsaddrALUwdrd2clkInst.GPRszrdataMemoryDataImmMemoryExtwdataALUControlOp

5、CodeRegDstExtSelOpSelBSrczero?5HardwiredControlTableOpcodeExtSelBSrcOpSelMemWRegWWBSrcRegDstPCSrcALU*RegFuncnoyesALUrdpc+4ALUisExtImmOpnoyesALUrtpc+416ALUiuuExtImmOpnoyesALUrtpc+416LWsExtImm+noyesMemrtpc+416SWsExt16Imm+yesno**pc+4BEQZz=0sExt16*0?nono**brBEQZz=1sExt16*0?nono**pc+4J***nono**jabsJA

6、L***noyesPCR31jabsJR***nono**rindJALR***noyesPCR31rindBSrc=Reg/ImmWBSrc=ALU/Mem/PCRegDst=rt/rd/R31PCSrc=pc+4/br/rind/jabs6PipelinedDatapath0x4Addwers1rs2PCaddrrd1werdataIRwsaddrwdrd2ALUGPRsrdataDataInst.MemoryImmMemoryExtwdatawritefetchdecode&Reg-fetchexecutememory-backphasephasephasephasephaseC

7、lockperiodcanbereducedbydividingtheexecutionofaninstructionintomultiplecyclest>max{t,t,t,t,t}(=tprobably)CIMRFALUDMRWDMHowever,CPIwillincreaseunlessinstructionsarepipelined7“IronLaw”ofProcessorPerformanceTime=InstructionsCyc